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31. 发明申请

US20070300200A1 Integrated circuit design system 有权
标题翻译：集成电路设计系统
公开(公告)号：US20070300200A1
公开(公告)日：2007-12-27
申请号：US11475675
申请日：2006-06-26
申请人： Christine Hau-Riege , Amit P. Marathe
发明人： Christine Hau-Riege , Amit P. Marathe
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.
摘要翻译：本发明提供了一种集成电路设计系统，其包括在计算机系统中提供设计系统，提供耦合到设计系统的布局设计工具，其中布局设计工具创建互连结构以满足电迁移标准，以及操纵设计数据库在设计系统内。

32. 发明授权

US07288782B1 Use of Ta-capped metal line to improve formation of memory element films 有权
标题翻译：使用钽盖金属线改善记忆元素膜的形成
公开(公告)号：US07288782B1
公开(公告)日：2007-10-30
申请号：US11251291
申请日：2005-10-14
申请人： Steven C. Avanzino , Amit P. Marathe
发明人： Steven C. Avanzino , Amit P. Marathe
IPC分类号： H01L47/00
CPC分类号： H01L21/76843 , H01L21/76852 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/16
摘要： Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
摘要翻译：公开了用于沉积用于半导体器件的改进的存储元件膜的方法。所述方法包括在要放置通孔的半导体衬底的金属线的上表面上提供硬掩模，基本上在除了要放置通孔之外的所有上表面中蚀刻掩模，沉积含Ta的覆盖层在除了要放置通孔的表面之外的基本上所有的金属线表面上，抛光含Ta的封盖层，以在露出金属线在通孔形成表面的同时产生一个镶嵌的含Ta盖，沉积介电层，电介质层以形成通孔，以及沉积存储元件膜。本发明的改进的Ta-Cu界面缓和了和/或消除了金属线顶表面下的介质层下存储元件膜的横向生长和铜空隙化，从而提高了半导体器件的可靠性和性能。

33. 发明授权

US06825684B1 Hot carrier oxide qualification method 失效
标题翻译：热载体氧化物鉴定方法
公开(公告)号：US06825684B1
公开(公告)日：2004-11-30
申请号：US10165879
申请日：2002-06-10
申请人： Hyeon-Seag Kim , Amit P. Marathe , Nian Yang , Tien-Chun Yang
发明人： Hyeon-Seag Kim , Amit P. Marathe , Nian Yang , Tien-Chun Yang
IPC分类号： G01R3100
CPC分类号： G01R31/287 , H01L22/20
摘要： A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.
摘要翻译：公开了一种为半导体器件生成寿命投影的方法。所公开的方法包括在多于一个应力条件下从多个半导体器件收集寿命信息。该方法还包括在每个应力条件下确定半导体器件的中值寿命。此外，该方法包括计算在预定百分比的装置将超过的每个应力条件下的寿命，并且对在操作条件下使用的装置的寿命进行推断。

34. 发明授权

US06822437B1 Interconnect test structure with slotted feeder lines to prevent stress-induced voids 失效
标题翻译：互连测试结构与开槽馈线，以防止应力引起的空隙
公开(公告)号：US06822437B1
公开(公告)日：2004-11-23
申请号：US10361239
申请日：2003-02-10
申请人： Christine Hau-Riege , John Sanchez , Amit P. Marathe
发明人： Christine Hau-Riege , John Sanchez , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L22/34
摘要： An interconnect test structure for characterizing electromigration includes a test line and a feeder coupled to the test line by a via structure. A width of the feeder line is greater than a width of the test line. Slots are formed in the feeder line for preventing formation of a stress-induced void at an interface between the feeder line and the via structure. Thus, an increase in resistance of the test structure is attributable to electromigration failure of the test line.
摘要翻译：用于表征电迁移的互连测试结构包括通过通孔结构连接到测试线的测试线和馈线。馈线的宽度大于测试线的宽度。在馈线中形成槽，用于防止在馈线和通孔结构之间的界面处形成应力引起的空隙。因此，测试结构的电阻增加归因于测试线的电迁移故障。

35. 发明授权

US06762597B1 Structure, system, and method for assessing electromigration permeability of layer material within interconnect 失效
标题翻译：用于评估互连中层材料的电迁移渗透性的结构，系统和方法
公开(公告)号：US06762597B1
公开(公告)日：2004-07-13
申请号：US10283625
申请日：2002-10-30
申请人： Christine Hau-Riege , Stefan Hau-Riege , Amit P. Marathe
发明人： Christine Hau-Riege , Stefan Hau-Riege , Amit P. Marathe
IPC分类号： G01R3126
CPC分类号： H01L23/5226 , G01R31/2853 , G01R31/2858 , H01L22/32 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： For determining electromigration permeability of a layer material, a test line, a feeder line, and a cathode line of an interconnect test structure are formed with current flowing from the test line through the feeder line to the cathode line. A no-flux structure is disposed between the cathode line and the feeder line, and the layer material is disposed between the feeder line and the test line. A respective current density and length product of the feeder line and the test line is respectively less than and greater than a respective critical Blech length constant. An occurrence of a void within the feeder line or the test line indicates that the layer material is permeable or impermeable.
摘要翻译：为了确定层材料的电迁移渗透性，形成互连测试结构的测试线，馈线和阴极线，电流从测试线通过馈线线路流到阴极线。在阴极线和馈电线之间设置无焊剂结构，并且层材料设置在馈电线和测试线之间。馈电线和测试线的相应电流密度和长度乘积分别小于和大于相应的临界Blech长度常数。供料线或试验线内的空隙出现表明层材料是可渗透的或不可渗透的。

36. 发明授权

US06717266B1 Use of an alloying element to form a stable oxide layer on the surface of metal features 有权
标题翻译：使用合金元素在金属表面上形成稳定的氧化物层
公开(公告)号：US06717266B1
公开(公告)日：2004-04-06
申请号：US10175393
申请日：2002-06-18
申请人： Amit P. Marathe , Darrell M. Erb
发明人： Amit P. Marathe , Darrell M. Erb
IPC分类号： H01L2348
CPC分类号： H01L23/53238 , H01L21/76886 , H01L21/76888 , H01L2924/0002 , H01L2924/00
摘要： The electromigration resistance of planarized metallization patterns, for example copper, inlaid in the surface of a layer of dielectric material, is enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one alloying layer comprising at least one alloying element for the metal of the features, and diffusing the at least one alloying element within the metallization features to effect alloying therewith. The at least one alloying element diffused within the metallization features, under conditions wherein an oxide layer forms on the surface of the metallization features, forms a stable oxide layer on the surface of the metallization features. The stable oxide layer reduces electromigration from the metallization features along the oxide layer.
摘要翻译：通过包括在金属化特征和电介质层的平坦化的上表面上覆盖沉积至少一种合金化的方法来增强镶嵌在介电材料层的表面中的平坦化金属化图案（例如铜）的电迁移阻力该层包括用于特征金属的至少一个合金元素，并且将金属化特征内的至少一个合金元素扩散以实现与其的合金化。在其中在金属化特征的表面上形成氧化物层的条件下，在金属化特征内扩散的至少一种合金元素在金属化特征的表面上形成稳定的氧化物层。稳定的氧化物层减少沿着氧化物层的金属化特征的电迁移。

37. 发明授权

US06649511B1 Method of manufacturing a seed layer with annealed region for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的具有退火区域的种子层的制造方法
公开(公告)号：US06649511B1
公开(公告)日：2003-11-18
申请号：US10272760
申请日：2002-10-16
申请人： Krishnashree Achuthan , Amit P. Marathe
发明人： Krishnashree Achuthan , Amit P. Marathe
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A manufacturing method provides a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.
摘要翻译：制造方法提供具有半导体器件的半导体衬底。在半导体衬底上形成有介质层和设置在其中的开口。阻挡层对开口进行排列，并且沉积种子层以使阻挡层成线。导体芯填充阻挡层上的开口以形成导体通道。种子层被退火以形成退火区域，其将种子层牢固地结合到阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

38. 发明授权

US06531777B1 Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP 失效
标题翻译：屏蔽金属完整性测试采用双层线对线路泄漏测试模式和部分CMP
公开(公告)号：US06531777B1
公开(公告)日：2003-03-11
申请号：US09599839
申请日：2000-06-22
申请人： Christy Mei-Chu Woo , Amit P. Marathe
发明人： Christy Mei-Chu Woo , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L22/14 , H01L22/34
摘要： A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing leakage or other electrical measurements between copper features on two different metal levels.
摘要翻译：一种用于确定集成电路制造中多级铜金属化结构的阻挡层完整性的结构和方法。新的测试结构防止铜CMP的任何导电残余物扩散到电介质层中。通过在两个不同的金属层上的铜特征之间执行泄漏或其他电气测量来测试阻挡层的完整性。

39. 发明授权

US08022716B2 Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance 有权
标题翻译：使用交流（AC）电容的介质击穿寿命增强
公开(公告)号：US08022716B2
公开(公告)日：2011-09-20
申请号：US12506837
申请日：2009-07-21
申请人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
发明人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
IPC分类号： G01R31/12
CPC分类号： G01R31/2623
摘要： A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.
摘要翻译：基于电容的突然变化来确定半导体器件中的电介质层的击穿时间。在半导体器件上施加大于该器件的工作电压的大小的交变电压，在施加电压期间在电介质层两端测量电容，直到发生电容的突然变化，从而表明电介质中的击穿层，并且击穿时间被缩放到工作电压。

40. 发明授权

US07451411B2 Integrated circuit design system 有权
标题翻译：集成电路设计系统
公开(公告)号：US07451411B2
公开(公告)日：2008-11-11
申请号：US11475675
申请日：2006-06-26
申请人： Christine Hau-Riege , Amit P. Marathe
发明人： Christine Hau-Riege , Amit P. Marathe
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides an integrated circuit design system, comprising providing a design system in a computer system, providing a layout design tool coupled to the design system, wherein the layout design tool creates an interconnect structure to satisfy electromigration criteria, and manipulating a design database within the design system.
摘要翻译：本发明提供了一种集成电路设计系统，包括在计算机系统中提供设计系统，提供耦合到设计系统的布局设计工具，其中布局设计工具创建互连结构以满足电迁移标准，以及操纵设计数据库在设计系统内。

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