专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US4903196A Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor 失效
标题翻译：用于保证复合多执行单元单处理器通用寄存器中数据的逻辑完整性的方法和装置
公开(公告)号：US4903196A
公开(公告)日：1990-02-20
申请号：US859156
申请日：1986-05-02
申请人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
发明人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384
摘要： A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the GPR sequentially or different GPR's concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed.A series of special purpose tags are associated with each GPR and execution unit. These tags are used together with control circuitry both within the GPR's, within the individual execution units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.
摘要翻译：一种用于通过包括单个CPU内的多个执行单元的高端机器配置来控制对其通用寄存器（GPR）的访问的方法和装置。本发明允许最多“N”个执行单元同时使用GPR顺序地或不同的GPR作为SINK或SOURCE同时执行“N”个指令，同时保持提供给执行单元的数据的逻辑完整性。如果仅执行顺序操作，则本发明的使用允许在执行指令时更高程度的并行性。一系列专用标签与每个GPR和执行单元相关联。这些标签与GPR内的各个执行单元内和指令解码单元内的控制电路一起使用，这允许在保持必要的逻辑完整性的同时多次使用寄存器。

32. 发明授权

US4823259A High speed buffer store arrangement for quick wide transfer of data 失效
标题翻译：高速缓冲存储布置，可快速传输数据
公开(公告)号：US4823259A
公开(公告)日：1989-04-18
申请号：US213506
申请日：1988-06-23
申请人： Frederick J. Aichelmann, Jr. , Rex H. Blumberg , David Meltzer , James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
发明人： Frederick J. Aichelmann, Jr. , Rex H. Blumberg , David Meltzer , James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897
摘要： A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.
摘要翻译：用于具有分级布置的多个高速缓存存储单元的数据处理系统中的高速缓冲存储装置允许宽数据块的快速传送。在每个缓存芯片上，集成了输入和输出锁存器，从而避免了单独的中间缓冲。输入和输出锁存器通过64字节的宽数据总线互连，使得数据块可以从一个缓存层次级别快速移动到另一个高速缓存层级。从输出到输入锁存器的芯片内部反馈连接允许数据块在读取之后被选择性地重新进入高速缓存。提供了一个附加的寄存器阵列，使得在从高速缓存传送到主存储器或CPU之后再次可以提供数据块，而不访问相应的高速缓存。广泛的数据块可以在一个周期内传输，从而在传输操作中减少高速缓存，从而增加可用性。

33. 发明授权

US4807110A Prefetching system for a cache having a second directory for sequentially accessed blocks 失效
标题翻译：用于具有用于顺序访问的块的第二目录的高速缓存的预取系统
公开(公告)号：US4807110A
公开(公告)日：1989-02-21
申请号：US597801
申请日：1984-04-06
申请人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
发明人： James H. Pomerene , Thomas R. Puzak , Rudolph N. Rechtschaffen , Frank J. Sparacio
IPC分类号： G06F12/08 , G06F9/38 , G06F12/12
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory. When an information block is accessed, a parent identifier derived from the block address is stored in a first level of the shadow directory. The address of a subsequently accessed block is stored in the second level of the shadow directory, in a position associated with the first-level position of the respective parent identifier.With each access to an information block, a check is made whether the respective parent identifier is already stored in the first level of the shadow directory. If it is found, then a descendant address from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids, with a high probability, the occurrence of cache misses.
摘要翻译：具有高速缓存的系统的预取机制除了普通高速缓存目录之外还具有两级影子目录。当访问信息块时，从块地址导出的父标识符被存储在影子目录的第一级中。随后访问的块的地址被存储在与目标父标识符的第一级位置相关联的位置中的影子目录的第二级。通过对信息块的每次访问，检查相应的父标识符是否已经存储在影子目录的第一级中。如果找到，那么来自相关联的二级位置的后代地址如果不存在于高速缓存中则被用于将信息块预取到高速缓存。这种机制很可能避免了高速缓存未命中的发生。

34. 发明授权

US09189403B2 Selective cache-to-cache lateral castouts 有权
标题翻译：选择性高速缓存到缓存横向转义
公开(公告)号：US09189403B2
公开(公告)日：2015-11-17
申请号：US12650018
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

35. 发明授权

US08015364B2 Method and apparatus for filtering snoop requests using a scoreboard 有权
标题翻译：使用记分板过滤窥探请求的方法和装置
公开(公告)号：US08015364B2
公开(公告)日：2011-09-06
申请号：US12129289
申请日：2008-05-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

36. 发明申请

US20080294850A1 METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING A SCOREBOARD 有权
标题翻译：使用分光镜过滤SNOOP要求的方法和装置
公开(公告)号：US20080294850A1
公开(公告)日：2008-11-27
申请号：US12129289
申请日：2008-05-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

37. 发明授权

US06311253B1 Methods for caching cache tags 失效
标题翻译：高速缓存标记缓存方法
公开(公告)号：US06311253B1
公开(公告)日：2001-10-30
申请号：US09336953
申请日：1999-06-21
申请人： Albert Chang , Mark Charney , Robert K. Montoye , Thomas R. Puzak
发明人： Albert Chang , Mark Charney , Robert K. Montoye , Thomas R. Puzak
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F12/0864
摘要： A method for storing information in a computer memory system includes maintaining an Mth level storage system including an Mth level data store for storing data, an Mth level full directory for storing a set of tags corresponding to the data, and an Mth level partial directory for storing a subset of the tags. The partial directory is accessible faster than the full directory. Upon an M-1 level miss corresponding to a request for data, a congruence class corresponding to the request is fetched from the partial directory when it is present therein; otherwise, it is fetched from the full directory. The requested data is retrieved from the data store when it is present in the congruence class; otherwise, it is retrieved from a next level of the memory system. The tags in the partial directory may be full tags, partial tags, or a combination thereof.
摘要翻译：一种用于在计算机存储器系统中存储信息的方法包括维护包括用于存储数据的第M级数据存储器的第M级存储系统，用于存储对应于数据的一组标签的第M级完整目录，以及用于存储标签的子集。部分目录可访问速度快于完整目录。在与数据请求相对应的M-1级丢失时，当存在对应于该请求的等同类时，从部分目录中取出; 否则，它将从完整目录中获取。当数据存储在同余类中时，从数据存储中检索所请求的数据; 否则，它从存储器系统的下一级检索。部分目录中的标签可以是完整标签，部分标签或其组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式