专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5355467A Second level cache controller unit and system 失效
标题翻译：二级缓存控制器单元和系统
公开(公告)号：US5355467A
公开(公告)日：1994-10-11
申请号：US208090
申请日：1994-03-08
申请人： Peter D. MacWilliams , Robert L. Farrell , Adalberto Golbert , Itzik Silas
发明人： Peter D. MacWilliams , Robert L. Farrell , Adalberto Golbert , Itzik Silas
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/6082
摘要： A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.
摘要翻译：实现为集成电路单元的第二级高速缓冲存储器控制器与辅助随机存取高速缓冲存储器和主存储器（系统）总线控制器一起操作以形成第二级高速缓存存储器子系统。该子系统与本地处理器（CPU）总线和主存储器总线接口，由总线提供独立的访问，从而当CPU所需的数据位于二级缓存中时，减少主存储器总线的流量。类似地，当主存储器总线的二级缓存访问被窃听并回写到主存储器时，CPU总线流量被最小化。与主存储器总线连接的监听锁存器通过次级高速缓存控制器单元中的高速缓存目录提供对高速缓冲存储器的窥探访问。控制器还支持使用最近使用（MRU）主存储器直写和流水线存储器总线周期请求的控制器标签阵列和二级缓存中的并行查找。

32. 发明授权

US4785396A Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit 失效
标题翻译：推挽串行总线耦合到多个具有冲突检测电路和仲裁电路的装置
公开(公告)号：US4785396A
公开(公告)日：1988-11-15
申请号：US148763
申请日：1988-01-26
申请人： Sean T. Murphy , Narjala Bhasker , Peter D. MacWilliams , Stephen J. Packer
发明人： Sean T. Murphy , Narjala Bhasker , Peter D. MacWilliams , Stephen J. Packer
IPC分类号： H04L12/413 , G06F13/40 , G06F11/00
CPC分类号： H04L12/413
摘要： A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques. A bus idle state occurs when all transmitters are off allowing both lines SDA and SDB be pulled high by pull-up resistors. Valid data states may occur any time a single transmitter is transmitting. When two or more transmitters begin transmitting a collision state exists. The message controller recognizes collisions and provides a back-off algorithm.
摘要翻译：公开了一种高速串行总线具有用于在多处理器计算机系统中传递消息的特定应用。串行总线包括具有被标识为“SDA”，“SDB”和“地”的线的三线串行链路。地线为耦合到串行总线的所有设备提供了通用参考。消息控制器耦合到每个代理，用于沿总线发送和接收串行数据。串行总线和地线的两条线都耦合到提供三个基本信号输出的消息控制器中的总线状态检测器。总线状态检测器确定总线是否在使用中，消息之间是否发生冲突，并且解码在总线上接收的数据。沿着串行总线发送的数据在相互之间相差180度的线SDA和SDB上驱动。消息控制器在本实施例中使用众所周知的曼彻斯特编码技术对要发送的消息进行编码。当所有发送器关闭时，总线空闲状态发生，允许通过上拉电阻将SDA和SDB两个线拉高。有效的数据状态可能在单个发射机发射时发生。当两个或多个发射机开始发送时，存在冲突状态。消息控制器识别冲突并提供退避算法。

33. 发明授权

US06598103B2 Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system 有权
公开(公告)号：US06598103B2
公开(公告)日：2003-07-22
申请号：US09991626
申请日：2001-11-06
申请人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
发明人： Peter D. MacWilliams , William S. Wu , Dilip K. Sampath , Bindi A. Prasad
IPC分类号： G06F1342
CPC分类号： G06F13/385 , G06F13/4018 , G06F13/405
摘要： A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

34. 发明授权

US06477614B1 Method for implementing multiple memory buses on a memory module 有权
标题翻译：在存储器模块上实现多个存储器总线的方法
公开(公告)号：US06477614B1
公开(公告)日：2002-11-05
申请号：US09658293
申请日：2000-09-08
申请人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
发明人： Michael W. Leddige , Bryce D. Horine , Randy Bonella , Peter D. MacWilliams
IPC分类号： G06F1206
CPC分类号： G06F13/4256
摘要： A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.
摘要翻译：计算机系统存储器模块包括双向中继器集线器，其在第一方向上将第一端口中的存储器总线信号作为输入，再生存储器信号，并将第二端口处的再生存储器信号作为至少一个单独的信号，用于耦合到存储器总线，用于每个再生的分离信号。在第二方向上，双向中继器集线器在第二端口处输入至少一个存储器总线信号，再生每个输入存储器总线信号，并在第一端口处输出再生的存储器信号以耦合到存储器总线。一种方法包括确定信号被寻址的存储器件是否在第一存储器模块上。如果存储器位于第一存储器模块上，则信号被路由到连接到存储器设备的第一存储器模块上的第一存储器总线。如果存储设备不在第一个存储器模块上，则信号被路由到第二存储器模块上的第二存储器总线。

35. 发明授权

US06192459B1 Method and apparatus for retrieving data from a data storage device 失效
公开(公告)号：US06192459B1
公开(公告)日：2001-02-20
申请号：US09046941
申请日：1998-03-23
申请人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
发明人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
IPC分类号： G00F1200
CPC分类号： G06F12/0864 , G06F12/0879
摘要： A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

36. 发明授权

US6012118A Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus 失效
标题翻译：在使用延迟回复的计算机系统中执行总线操作的方法和装置，不使用地址总线
公开(公告)号：US6012118A
公开(公告)日：2000-01-04
申请号：US954442
申请日：1997-10-20
申请人： Muthurajan Jayakumar , Sunny C. Huang , Peter D. MacWilliams , William S. Wu , Stephen Pawlowski , Bindi A. Prasad
发明人： Muthurajan Jayakumar , Sunny C. Huang , Peter D. MacWilliams , William S. Wu , Stephen Pawlowski , Bindi A. Prasad
IPC分类号： G06F13/37 , G06F13/42
CPC分类号： G06F13/37 , G06F13/4252
摘要： A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.
摘要翻译：计算机系统中的分流事务总线，其允许使用附加总线以流水线方式进行无序回复以用于响应阶段。

37. 发明授权

US5651137A Scalable cache attributes for an input/output bus 失效
标题翻译：输入/输出总线的可扩展缓存属性
公开(公告)号：US5651137A
公开(公告)日：1997-07-22
申请号：US420494
申请日：1995-04-12
申请人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
发明人： Peter D. MacWilliams , Norman J. Rasmussen , Nicholas D. Wade , William S. F. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
摘要翻译：介绍了高速外设总线的内存总线扩展。具体来说，边带信号用于将高速缓存属性映射，高速缓存一致性周期和双处理器支持的高级机制覆盖到高速外设总线上。在高速缓存属性映射的情况下，先前处理器和高速缓存中支持的三个高速缓存存储器属性信号被保持三个原始信号的所有功能的两个高速缓存属性信号所取代。在缓存一致性周期的情况下，提供高级操作模式。这些包括支持快速写入，通过缓存对完全高速缓存行写入的写回数据的丢弃以及允许高速缓存提供响应于存储器读取的数据的读取干预。在双处理器支持的情况下，呈现了用于支持双处理器的几个新信号和相关协议。具体支持分为以下三个方面：扩展侦听以支持多个缓存，支持两个处理器之间的共享数据，以及提供处理器和升级仲裁协议，允许双处理器共享一个授权信号线。

38. 发明授权

US5455957A Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol 失效
标题翻译：用于通过事务确定性请求/响应协议使用事务来执行计算机系统的两个时钟独立总线代理之间的总线事务的方法和装置
公开(公告)号：US5455957A
公开(公告)日：1995-10-03
申请号：US394560
申请日：1995-02-27
申请人： Stephen Pawlowski , Peter D. MacWilliams
发明人： Stephen Pawlowski , Peter D. MacWilliams
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08 , G06F13/16 , G06F13/42 , G06F13/00
CPC分类号： G06F12/0684 , G06F12/0653 , G06F12/0888
摘要： An apparatus and method for communicating characteristics about a memory module to a processor unit. A method and apparatus for communicating memory module characteristics, such as whether the module can communicate in a deterministic mode, memory size, memory speed, memory type and whether the memory is cachable to a processor. In the present invention, the processor asserts a request signal onto the system bus and the memory module corresponding to the address of the request respond with information regarding its characteristics.
摘要翻译：一种用于将存储器模块的特性传送到处理器单元的装置和方法。用于传达存储器模块特性的方法和装置，例如模块是否可以以确定性模式进行通信，存储器大小，存储器速度，存储器类型以及存储器是否可高速缓存到处理器。在本发明中，处理器将请求信号置于系统总线上，并且与该请求的地址对应的存储器模块响应关于其特性的信息。

39. 发明授权

US5301299A Optimized write protocol for memory accesses utilizing row and column strobes 失效
标题翻译：使用行和列选通的存储器访问优化的写协议
公开(公告)号：US5301299A
公开(公告)日：1994-04-05
申请号：US20184
申请日：1993-02-16
申请人： Stephen Pawlowski , Peter D. MacWilliams
发明人： Stephen Pawlowski , Peter D. MacWilliams
IPC分类号： G06F12/02 , G11C8/18 , G06F12/08
CPC分类号： G11C8/18 , G06F12/0215
摘要： An improved method for accessing memory in a computer system using standard fast paged mode memory access for a second memory access where the second memory access is pending at the completion of a first memory access. However, if at the completion of a first memory access there is no pending memory request, the RAS line of the memory is deactivated allowing precharge during an idle state on the bus.
摘要翻译：一种用于在第二存储器访问中使用标准快速分页模式存储器访问的用于访问计算机系统中的存储器的改进方法，其中第二存储器访问在第一存储器访问完成时待处理。然而，如果在完成第一存储器访问时没有未决存储器请求，则存储器的RAS线被停用，允许在总线上的空闲状态期间预充电。

40. 发明授权

US06519735B1 Method and apparatus for detecting errors in data output from memory and a device failure in the memory 有权
标题翻译：用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置
公开(公告)号：US06519735B1
公开(公告)日：2003-02-11
申请号：US09217814
申请日：1998-12-22
申请人： Thomas J. Holman , Peter D. MacWilliams
发明人： Thomas J. Holman , Peter D. MacWilliams
IPC分类号： G11C2900
CPC分类号： G06F11/1028 , G06F11/1036
摘要： A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.
摘要翻译：一种用于检测从存储器输出的数据中的错误和存储器中的设备故障的方法和装置。在本发明中，基于要输入到存储器的数据生成校验码。检查码在等于零时有效。响应于写命令，校验码被反转并作为代码字与数据一起输入存储器。响应于读取命令，从存储器输出码字。从存储器输出的码字指示存储器中的设备是否失败。包括在从存储器输出的码字中的反转检查码被重新反转。指示基于包括校验码的数据和码字来生成包括在存储器输出的码字中的数据是否包含错误的信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式