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31. 发明授权

US6085277A Interrupt and message batching apparatus and method 失效
标题翻译：中断和消息批处理设备和方法
公开(公告)号：US6085277A
公开(公告)日：2000-07-04
申请号：US950755
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Shawn Michael Lambeth , Paul Edward Movall , Daniel Frank Moertl , Charles Scott Graham , William Joseph Armstrong , Thomas Rembert Sand
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/546
摘要： An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.
摘要翻译：中断和消息批处理设备和方法通过将I / O完成事件与单个处理器中断分组，以使I / O操作等待时间要求与处理器利用率要求平衡来优化，从而减少处理器中断和结果上下文切换的数量和频率整体计算机系统性能。本发明在I / O总线上从处理器复合体向I / O适配器发送消息，命令连接到I / O适配器的I / O设备执行功能。完成命令功能后，I / O适配器中的消息处理器会生成一条消息，并将其发送到I / O总线上的处理器复合体。该消息在存储器的消息队列中排队，消息计数被更新，并且当消息计数超过消息步调计数时以及何时发送处理器复杂中断。如果消息具有相对较高的延迟，或者如果消息具有相对低的延迟，则信令定时器也可以被编程为具有快速的响应时间值。当消息排入队列时，启动信令定时器，然后当消息计数超过消息起搏计数或信令定时器过去时，信号通知处理器复杂中断。

32. 发明授权

US6078970A System for determining adapter interrupt status where interrupt is sent to host after operating status stored in register is shadowed to host memory 失效
标题翻译：用于确定适配器中断状态的系统，其中存储在寄存器中的操作状态后中断发送到主机被遮蔽到主机存储器
公开(公告)号：US6078970A
公开(公告)日：2000-06-20
申请号：US951157
申请日：1997-10-15
申请人： Gregory Michael Nordstrom , Daniel Frank Moertl , Thomas Rembert Sand
发明人： Gregory Michael Nordstrom , Daniel Frank Moertl , Thomas Rembert Sand
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An I/O adapter connects an I/O adapter to an I/O bus and includes a device interrupt status register and an interrupt status shadow address register. The device interrupt status register stores the interrupt status of the I/O adapter. The I/O adapter accesses the interrupt status shadow address register to determine an address of main memory at which the device interrupt status register is shadowed. After shadowing the interrupt status, the I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status. A multifunction I/O adapter permits a plurality of I/O adapters to be connected thereto and includes a function interrupt status register to summarize the interrupt status of all the I/O adapters attached thereto. After shadowing the summarized interrupt status, the multifunction I/O adapter interrupts the processor complex which may then access local, main memory to determine the interrupt status.
摘要翻译： I / O适配器将I / O适配器连接到I / O总线，并包括一个设备中断状态寄存器和一个中断状态影子地址寄存器。器件中断状态寄存器存储I / O适配器的中断状态。 I / O适配器访问中断状态阴影地址寄存器，以确定器件中断状态寄存器被遮蔽的主存储器的地址。在遮蔽中断状态后，I / O适配器中断处理器复合体，然后可以访问本地主存储器以确定中断状态。多功能I / O适配器允许多个I / O适配器连接到其上，并且包括功能中断状态寄存器，以总结所附加到其上的所有I / O适配器的中断状态。在遮蔽总结的中断状态之后，多功能I / O适配器中断处理器复合体，然后可以访问本地主存储器以确定中断状态。

33. 发明授权

US08234520B2 Wear leveling of solid state disks based on usage information of data and parity received from a raid controller 有权
标题翻译：根据从RAID控制器接收到的数据和奇偶校验的使用信息，固态硬盘的硬化水平
公开(公告)号：US08234520B2
公开(公告)日：2012-07-31
申请号：US12561210
申请日：2009-09-16
申请人： Andrew Dale Walls , Daniel Frank Moertl
发明人： Andrew Dale Walls , Daniel Frank Moertl
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/108 , G06F3/0616 , G06F3/0688 , G06F11/1068 , G06F11/1092 , G06F12/0246 , G06F2211/1057 , G06F2211/1088 , G06F2212/7208 , G06F2212/7211 , G11C16/349
摘要： A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure. The controller sends the data structures to the plurality of solid state disks, wherein the plurality of solid state disks allocate a storage area that is estimated to have a relatively greater life expectancy in comparison to other storage areas to store the block that includes the parity information.
摘要翻译：控制器将多个固态磁盘配置为独立磁盘（RAID）的冗余阵列，其中所述多个固态磁盘存储多个块，并且其中所述多个固态磁盘的存储区域对应于至少一些块的多个块具有不同量的预期寿命。控制器包括与要存储在多个固态磁盘的存储区域中的块相关联的数据结构，该指示包括对应于该RAID的奇偶校验信息，其中奇偶校验信息包括对应于错误校正机制的信息以防止磁盘故障。控制器将数据结构发送到多个固态磁盘，其中多个固态磁盘分配与其他存储区域相比估计具有相对较大寿命的存储区域以存储包括奇偶校验信息的块。

34. 发明申请

US20110066882A1 WEAR LEVELING OF SOLID STATE DISKS BASED ON USAGE INFORMATION OF DATA AND PARITY RECEIVED FROM A RAID CONTROLLER 有权
标题翻译：基于从RAID控制器接收到的数据和奇偶性的使用信息，固定状态磁盘的磨损
公开(公告)号：US20110066882A1
公开(公告)日：2011-03-17
申请号：US12561210
申请日：2009-09-16
申请人： Andrew Dale Walls , Daniel Frank Moertl
发明人： Andrew Dale Walls , Daniel Frank Moertl
IPC分类号： G06F11/20 , G06F11/00 , G06F12/00 , G06F11/10 , G06F13/28 , G06F13/00 , G06F12/14 , G06F12/06
CPC分类号： G06F11/108 , G06F3/0616 , G06F3/0688 , G06F11/1068 , G06F11/1092 , G06F12/0246 , G06F2211/1057 , G06F2211/1088 , G06F2212/7208 , G06F2212/7211 , G11C16/349
摘要： A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure. The controller sends the data structures to the plurality of solid state disks, wherein the plurality of solid state disks allocate a storage area that is estimated to have a relatively greater life expectancy in comparison to other storage areas to store the block that includes the parity information.
摘要翻译：控制器将多个固态磁盘配置为独立磁盘（RAID）的冗余阵列，其中所述多个固态磁盘存储多个块，并且其中所述多个固态磁盘的存储区域对应于至少一些块的多个块具有不同量的预期寿命。控制器包括与要存储在多个固态磁盘的存储区域中的块相关联的数据结构，该指示包括对应于该RAID的奇偶校验信息，其中奇偶校验信息包括对应于错误校正机制的信息以防止磁盘故障。控制器将数据结构发送到多个固态磁盘，其中多个固态磁盘分配与其他存储区域相比估计具有相对较大寿命的存储区域以存储包括奇偶校验信息的块。

35. 发明申请

US20080294841A1 APPARATUS FOR IMPLEMENTING ENHANCED VERTICAL ECC STORAGE IN A DYNAMIC RANDOM ACCESS MEMORY 失效
标题翻译：在动态随机访问存储器中实现增强的垂直ECC存储的设备
公开(公告)号：US20080294841A1
公开(公告)日：2008-11-27
申请号：US12168971
申请日：2008-07-08
申请人： Michael Joseph Carnevale , Steven B. Herndon , Daniel Frank Moertl
发明人： Michael Joseph Carnevale , Steven B. Herndon , Daniel Frank Moertl
IPC分类号： G06F12/06
CPC分类号： G06F11/1044
摘要： A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.
摘要翻译：提供了一种用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置。动态随机存取存储器（DRAM）被分成多个组。每个组都驻留在DRAM行地址选通（RAS）页面中，从而可以访问组内的多个位置，而不会引起额外的RAS访问损失。每个组在逻辑上分成多个段，用于存储具有用于存储数据段的ECC的至少一个段的数据。对于写入操作，将数据写入数据段，然后将ECC用于数据写入ECC段。对于读取操作，从ECC段读取ECC，然后从数据段读取数据。

36. 发明授权

US07133943B2 Method and apparatus for implementing receive queue for packet-based communications 有权
标题翻译：实现基于分组通信的接收队列的方法和装置
公开(公告)号：US07133943B2
公开(公告)日：2006-11-07
申请号：US10374256
申请日：2003-02-26
申请人： Michael Joseph Carnevale , Daniel Frank Moertl
发明人： Michael Joseph Carnevale , Daniel Frank Moertl
IPC分类号： G06F3/06
CPC分类号： H04L1/1607 , H04L49/90 , H04L49/901 , H04L49/9063 , H04L49/9073 , H04L49/9094
摘要： A receiver for an InfiniBand network contains a buffer and a control memory. A set of pointers for receive queues in the buffer is maintained in the control memory. Two independent queues exist for incoming messages from a given source, one for writes and the other for reads. The receiver controls the various queue pointers to generate appropriate acknowledgments and negative acknowledgment messages, and to transfer data as required to and from the host over an internal bus. Preferably, the receiver delays acknowledging certain write requests if requests are pending on the read queue. Preferably, the control memory and the major control functions of the receiver are implemented in hardware on a ASIC chip.
摘要翻译： InfiniBand网络的接收器包含缓冲区和控制存储器。缓冲器中的接收队列的一组指针被保存在控制存储器中。存在来自给定源的输入消息的两个独立队列，一个用于写入，另一个用于读取。接收器控制各种队列指针以产生适当的确认和否定确认消息，并根据需要通过内部总线将数据传送到主机和从主机传输数据。优选地，如果读取队列上的请求正在等待，则接收器延迟确认某些写入请求。优选地，控制存储器和接收器的主要控制功能在ASIC芯片上以硬件实现。

37. 发明授权

US06909315B2 Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) 失效
标题翻译：用于高速动态随机存取存储器（DRAM）的数据选通信号（DQS）
公开(公告)号：US06909315B2
公开(公告)日：2005-06-21
申请号：US10102274
申请日：2002-03-20
申请人： Michael Frank Carnevale , Paul Allen Ganfield , Daniel Frank Moertl
发明人： Michael Frank Carnevale , Paul Allen Ganfield , Daniel Frank Moertl
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4076 , G11C29/02 , H03H11/26
CPC分类号： G11C29/028 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50012 , G11C2207/2254
摘要： Embodiments are provided in which a method for delaying a strobe signal for a first pre-specified amount of time is described. A test signal is sent through a first number of delay books and a test is done as to whether it takes the test signal approximately a second pre-specified amount of time to pass the first number of delay books. Then, the number of delay books is increased or decreased by one at a time and until the number of delay books reaches a second number where it takes the test signal approximately the second pre-specified amount of time to pass the second number of delay books. From the second number, a third number of delay books is determined which is needed to cause a propagation delay approximately equal to the first pre-specified amount of time. Finally, the strobe signal is passed through the third number of delay books.
摘要翻译：提供了一种用于延迟第一预定时间量的选通信号的方法的实施例。通过第一数量的延迟书发送测试信号，并且测试是否将测试信号大约第二预定的时间量通过第一数量的延迟书。然后，延迟书的数量一次增加或减少，直到延迟书的数量达到第二个数字，其中测试信号大约第二个预定的时间量通过第二数量的延迟书。从第二个数字，确定第三数量的延迟书，其需要使传播延迟大致等于第一预先指定的时间量。最后，频闪信号通过第三数量的延迟书。

38. 发明授权

US06640277B1 Input staging logic for latching source synchronous data 有权
标题翻译：用于锁存源同步数据的输入分级逻辑
公开(公告)号：US06640277B1
公开(公告)日：2003-10-28
申请号：US10137059
申请日：2002-05-02
申请人： Daniel Frank Moertl
发明人： Daniel Frank Moertl
IPC分类号： G06F1342
CPC分类号： G06F5/06 , G06F13/4072
摘要： A circuit arrangement, program product and method in one aspect utilize three stage input staging logic to receive source synchronous data in a source synchronous communications system such as a PCI-compatible communication system. In another aspect, two stage input staging logic is supplemented by at least one holding latch disposed intermediate the output of the two stage input staging logic and a common clock synchronizing circuit to effectively increase the hold time of a staging latch in one of the latching stages prior to common clock synchronization. The holding latch may be clocked concurrently with at least one other staging latch in the input staging logic that is clocked later in a data phase than the staging latch that feeds the holding latch so that the data clocked into both such staging latches is available for common clock synchronization at roughly the same point in time.
摘要翻译：一方面的电路装置，程序产品和方法利用三级输入分级逻辑来在诸如PCI兼容通信系统的源同步通信系统中接收源同步数据。在另一方面，两级输入分级逻辑由至少一个保持锁存器来补充，所述至少一个保持锁存器设置在两级输入级别逻辑的输出端和公共时钟同步电路之间，以有效地增加锁存级之一上的分段锁存器的保持时间在公共时钟同步之前。保持锁存器可以与输入级别逻辑中的至少一个其他分段锁存器同时计时，该数据锁存器在与数据相位相比较的数据相位中被提前保持锁存器的分段锁存器进行计时，使得定时进入这两个分段锁存器的数据可用于共用时钟同步在大致相同的时间点。

39. 发明授权

US06353910B1 Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage 有权
标题翻译：在利用垂直ECC存储的动态随机存取存储器中实现纠错编码（ECC）的方法和装置
公开(公告)号：US06353910B1
公开(公告)日：2002-03-05
申请号：US09289336
申请日：1999-04-09
申请人： Michael Joseph Carnevale , Daniel Frank Moertl
发明人： Michael Joseph Carnevale , Daniel Frank Moertl
IPC分类号： G11C2900
CPC分类号： G06F11/1044
摘要： Methods and apparatus for implementing error correction coding (ECC) in a dynamic random access memory (DRAM) utilizing vertical ECC storage. An integral number of available data blocks is identified for each page of the DRAM. Each data block includes a defined number of data and ECC bytes. Data and ECC bytes are stored in the identified integral number of data blocks for each page. The remaining bytes in each page are used as padding.
摘要翻译：在利用垂直ECC存储的动态随机存取存储器（DRAM）中实现纠错编码（ECC）的方法和装置。为DRAM的每个页面标识可用数据块的整数。每个数据块包括定义数量的数据和ECC字节。数据和ECC字节存储在每个页面的已标识的整数数据块中。每页中的剩余字节用作填充。

40. 发明授权

US06233641B1 Apparatus and method of PCI routing in a bridge configuration 失效
标题翻译：在桥接配置中PCI路由的装置和方法允许独立使用总线
公开(公告)号：US06233641B1
公开(公告)日：2001-05-15
申请号：US09093441
申请日：1998-06-08
申请人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
发明人： Charles Scott Graham , Shawn Michael Lambeth , Daniel Frank Moertl , Paul Edward Movall
IPC分类号： G06F1338
CPC分类号： G06F13/4022 , G06F13/4045
摘要： A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.
摘要翻译： PCI扩展卡接口的主PCI总线和多个辅助PCI总线通过路由电路互连。路由电路通过将每个辅助PCI总线与地址范围相关联并将从主PCI总线接收的命令转发到辅助PCI总线映射，分别用作主PCI总线和每个辅助PCI总线之间的交换桥到包括命令地址的地址范围。此外，路由电路从辅助PCI总线转发用于主PCI总线的命令。此外，当从一个辅助PCI总线接收的命令用于另一个PCI总线时，路由电路直接在辅助PCI总线之间路由命令，而不使用主总线。因此，主PCI总线上的流量和延迟降低，效率提高。

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