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31. 发明申请

US20100178746A1 METHOD OF FABRICATING HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) 有权
标题翻译：制备异相双极晶体管（HBT）的方法
公开(公告)号：US20100178746A1
公开(公告)日：2010-07-15
申请号：US12732560
申请日：2010-03-26
申请人： Thomas N. Adam , Rajendran Krishnasamy
发明人： Thomas N. Adam , Rajendran Krishnasamy
IPC分类号： H01L21/8222
CPC分类号： H01L29/7371 , H01L21/82285 , H01L21/823878 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0826 , H01L27/1203 , H01L29/045
摘要： A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation in addition to silicon crystalline orientation to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation may be disposed on crystalline orientation . Alternatively, the region of silicon crystalline orientation may be disposed on crystalline orientation .
摘要翻译：公开了一种制造异质结双极晶体管（HBT）的方法，其中HBT具有结合设置在包含硅晶取向<110>的衬底上的异质结双极结构的结构。异质结双极结构可以包括发射极，基极和集电极。衬底可以包括浅沟槽隔离（STI）区域和设置有集电极的深沟槽区域。除了硅晶体取向<110>之外，衬底可以包括硅晶体取向<100>的区域，以通过使用混合取向技术（HOT）形成复合衬底。结晶取向区域<100>可以设置在晶体取向110上。或者，硅结晶取向区域<110>可以以结晶取向<100>设置。

32. 发明申请

US20090242949A1 CMOS IMAGE SENSOR WITH REDUCED DARK CURRENT 有权
标题翻译： CMOS图像传感器具有降低的电流
公开(公告)号：US20090242949A1
公开(公告)日：2009-10-01
申请号：US12056305
申请日：2008-03-27
申请人： James W. Adkisson , Rajendran Krishnasamy
发明人： James W. Adkisson , Rajendran Krishnasamy
IPC分类号： H01L31/113 , H01L31/18
CPC分类号： H01L27/14603
摘要： A carbon-containing semiconductor layer is formed on exposed surfaces of a p-doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.
摘要翻译：在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。随后形成浅沟槽隔离结构和光电二极管。现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

33. 发明授权

US07538004B2 Method of fabrication for SiGe heterojunction bipolar transistor (HBT) 失效
标题翻译： SiGe异质结双极晶体管（HBT）制造方法
公开(公告)号：US07538004B2
公开(公告)日：2009-05-26
申请号：US11937534
申请日：2007-11-09
申请人： Peter J. Geiss , Alvin J. Joseph , Rajendran Krishnasamy , Xuefeng Liu
发明人： Peter J. Geiss , Alvin J. Joseph , Rajendran Krishnasamy , Xuefeng Liu
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.
摘要翻译：在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。在基板上形成基极区域，在基极区域上形成发射极区域。集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。

34. 发明申请

US20080179632A1 SELECTIVE LINKS IN SILICON HETERO-JUNCTION BIPOLAR TRANSISTORS USING CARBON DOPING AND METHOD OF FORMING SAME 有权
标题翻译：使用碳掺杂的硅异质结双极晶体管中的选择性链接及其形成方法
公开(公告)号：US20080179632A1
公开(公告)日：2008-07-31
申请号：US12060615
申请日：2008-04-01
申请人： Thomas N. Adam , Rajendran Krishnasamy
发明人： Thomas N. Adam , Rajendran Krishnasamy
IPC分类号： H01L29/737
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242
摘要： Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.
摘要翻译：双极晶体管和形成双极晶体管的方法。该方法包括在硅衬底中形成P型集电体; 在集电体上形成本征碱，本征碱包括第一N型掺杂剂物质，锗和碳; 在本征基极的第一区域和第二区域上形成N型外部基极，在与集电体相邻的电介质上的集电极和第二区域之上的第一区域，含有或不含有碳的N型外部碱基; 以及在本征基底的第一区域上形成P型发射体。

35. 发明授权

US08853043B2 Silicon germanium (SiGe) heterojunction bipolar transistor (HBT) 有权
标题翻译：硅锗（SiGe）异质结双极晶体管（HBT）
公开(公告)号：US08853043B2
公开(公告)日：2014-10-07
申请号：US13610641
申请日：2012-09-11
申请人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
发明人： Wade J. Hodge , Alvin J. Joseph , Rajendran Krishnasamy , Qizhi Liu , Bradley A. Orner
IPC分类号： H01L21/331 , H01L21/8222 , H01L29/737 , H01L29/10 , H01L21/8249
CPC分类号： H01L29/7378 , H01L21/8249 , H01L29/1004
摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
摘要翻译：异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。外基的表面可以被硅化。

36. 发明授权

US07800147B2 CMOS image sensor with reduced dark current 有权
标题翻译：具有降低暗电流的CMOS图像传感器
公开(公告)号：US07800147B2
公开(公告)日：2010-09-21
申请号：US12056305
申请日：2008-03-27
申请人： James W. Adkisson , Rajendran Krishnasamy
发明人： James W. Adkisson , Rajendran Krishnasamy
IPC分类号： H01L31/068
CPC分类号： H01L27/14603
摘要： A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.
摘要翻译：在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。随后形成浅沟槽隔离结构和光电二极管。现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

37. 发明授权

US07767539B2 Method of fabricating patterned SOI devices and the resulting device structures 失效
标题翻译：制造图案化SOI器件的方法和所得到的器件结构
公开(公告)号：US07767539B2
公开(公告)日：2010-08-03
申请号：US11949973
申请日：2007-12-04
申请人： Robert J. Gauthier, Jr. , Rajendran Krishnasamy
发明人： Robert J. Gauthier, Jr. , Rajendran Krishnasamy
IPC分类号： H01L21/762
CPC分类号： H01L29/7848 , H01L21/26533 , H01L21/76243 , H01L21/76267 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.
摘要翻译：一种用于制造氧化硅（SOI）衬底上的集成电路的FET晶体管的方法和结果，包括以下步骤：在衬底上的栅极两侧的衬底中形成凹槽，将氧离子注入到凹槽中，并退火将氧离子转换成每个凹槽下方的SOI层的衬底。

38. 发明申请

US20100065922A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100065922A1
公开(公告)日：2010-03-18
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

39. 发明申请

US20100013973A1 PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY 有权
标题翻译：具有帧存储能力的像素传感器单元
公开(公告)号：US20100013973A1
公开(公告)日：2010-01-21
申请号：US12174289
申请日：2008-07-16
申请人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H04N5/37452 , H04N5/2355
摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.
摘要翻译：在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。

40. 发明申请

US20100013972A1 PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY 有权
公开(公告)号：US20100013972A1
公开(公告)日：2010-01-21
申请号：US12174264
申请日：2008-07-16
申请人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H04N5/37452
摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

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