专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08077812B2 Reduced-complexity multiple-input, multiple-output detection 有权
标题翻译：降低复杂度的多输入多输出检测
公开(公告)号：US08077812B2
公开(公告)日：2011-12-13
申请号：US12508697
申请日：2009-07-24
申请人： Nils Graef , Joachim S. Hammerschmdit
发明人： Nils Graef , Joachim S. Hammerschmdit
IPC分类号： H04L27/06
CPC分类号： H04L25/03191 , H04B7/0413 , H04L5/0023 , H04L25/0204 , H04L25/0224 , H04L25/0321 , H04L25/03318 , H04L27/2647 , H04L2025/03414 , H04L2025/03426 , H04L2025/03643
摘要： A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.
摘要翻译：无线接收机检测由多输入多输出（MIMO）发射机产生的信号。接收机对软输出信号检测应用最大似然检测（MLD），其中通过计算和累积例如连续候选测试的欧几里德度量之间的差异来递归地执行跨所有候选向量的MLD详尽搜索。用于积累的差异项也递归计算。采用诸如通过三角形波形排序的候选者的排序，使得在任何两个连续的候选评估之间仅改变一个候选变量，导致减少的计算集合。

32. 发明申请

US20110246862A1 HARD INPUT LOW DENSITY PARITY CHECK DECODER 有权
标题翻译：硬输入低密度奇偶校验解码器
公开(公告)号：US20110246862A1
公开(公告)日：2011-10-06
申请号：US12750871
申请日：2010-03-31
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H04L1/0057 , H03M13/1108 , H03M13/6502 , H04L1/0045
摘要： A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated. The exemplary method terminates based on a predefined syndrome output.
摘要翻译：提供了一种硬输入低密度奇偶校验解码器，其在位翻转解码器和综合征计算器之间共享逻辑。硬判决解码器解码一个或多个错误校正（EC）码字，并且包括翻转与一个或多个不满足的奇偶校验检查相关联的一个或多个比特节点的比特翻译解码器; 以及校正子计算器，执行奇偶校验以确定比特翻转解码器是否已经收敛在有效码字上，其中比特翻转解码器和辨识器计算器共享一个或多个逻辑元素。解码器可选地包括用于更新每个翻转位的奇偶校验等式的装置。通过翻转连接到一个或多个不满足的奇偶校验的一个或多个比特节点来解码错误校正（EC）码字; 以及每当所述一个或多个比特节点被翻转时，更新与所述一个或多个比特节点相关联的一个或多个奇偶校验方程。每当更新位时，更新奇偶校验方程。该示例性方法基于预定义的错误输出终止。

33. 发明授权

US08032818B2 Method and apparatus for storing survivor paths in a Viterbi detector using input-dependent pointer exchange 有权
标题翻译：用于使用输入相关指针交换在维特比检测器中存储幸存路径的方法和装置
公开(公告)号：US08032818B2
公开(公告)日：2011-10-04
申请号：US11241761
申请日：2005-09-30
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： H03M13/03
CPC分类号： H03M13/4184 , H03M13/395
摘要： Methods and apparatus are provided for storing survivor paths in a Viterbi detector. At least one register and at least one pointer are maintained for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. A trellis transition type is determined, for example, based on a decision from an add/compare/select unit. One or more predefined rules based on a trellis structure and the trellis transition type are employed to exchange one or more of the pointers and to update one or more of the at least one registers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a latch for storing one bit of a bit sequence associated with a Viterbi state.
摘要翻译：提供了用于在维特比检测器中存储幸存路径的方法和装置。为每个状态保持至少一个寄存器和至少一个指针。每个寄存器存储与维特比状态相关联的位序列，并且每个指针指向其中一个寄存器。网格转换类型例如基于来自加法/比较/选择单元的判定来确定。采用基于网格结构和网格转换类型的一个或多个预定义规则来交换一个或多个指针并更新至少一个寄存器中的一个或多个。还针对维特比检测器公开了幸存路径存储器。幸存者路径存储器包括多个列，每个列与不同的时间步长相关联，以及输入处理器。每列包括用于存储与维特比状态相关联的位序列的一位的锁存器。

34. 发明授权

US07730384B2 Method and apparatus for evaluating performance of a read channel 有权
标题翻译：用于评估读通道性能的方法和装置
公开(公告)号：US07730384B2
公开(公告)日：2010-06-01
申请号：US11068224
申请日：2005-02-28
申请人： Nils Graef , Zachary Keirn
发明人： Nils Graef , Zachary Keirn
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/47 , H03M13/3905 , H03M13/4146 , H03M13/612
摘要： Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.
摘要翻译：提供了用于测量读取通道的性能的方法和装置。诸如SOVA和最大后验（MAP）检测器的多种检测技术产生与比特决定相关联的比特决策和相应的可靠性值。与比特决定相关联的可靠性值可以例如以对数似然比（LLR）的形式表示。可靠性值可以被监视并用作性能测量。本发明提供了通常与BER直接相关的信道性能测量，但可以在较少的时间内收集。

35. 发明申请

US20100093393A1 Systems and Methods for Music Recognition 审中-公开
标题翻译：音乐识别系统与方法
公开(公告)号：US20100093393A1
公开(公告)日：2010-04-15
申请号：US12519523
申请日：2007-04-23
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： H04M1/00 , G06F17/00 , G10L15/00
CPC分类号： H04H60/74 , H04H60/40 , H04H60/43 , H04H60/58 , H04H60/65 , H04N21/8113
摘要： Various systems and methods for music recognition are disclosed herein. For example, music recognition devices are disclosed that include a data receiver that is operable to receive a data signal incorporating an identification of a currently playing song. The devices further include a memory and a processor. The memory includes instructions executable by the processor to: parse the data signal and to cause the identification to be stored to the memory. At least a portion of the identification is maintained in the memory after the currently playing song has terminated.
摘要翻译：本文公开了用于音乐识别的各种系统和方法。例如，公开了包括可操作以接收包含当前播放歌曲的标识的数据信号的数据接收器的音乐识别装置。这些设备还包括存储器和处理器。存储器包括可由处理器执行的指令：解析数据信号并使识别被存储到存储器中。在当前播放的歌曲已经终止之后，识别的至少一部分被保存在存储器中。

36. 发明申请

US20100070837A1 Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such 有权
标题翻译：基于功率减少的队列数据检测和解码系统及其使用方法
公开(公告)号：US20100070837A1
公开(公告)日：2010-03-18
申请号：US12270713
申请日：2008-11-13
申请人： Changyou Xu , Shaohua Yang , Hao Zhong , Nils Graef , Ching-Fu Wu
发明人： Changyou Xu , Shaohua Yang , Hao Zhong , Nils Graef , Ching-Fu Wu
IPC分类号： H04L1/00
CPC分类号： H04L1/0051 , H04L1/0057 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set. The second detector is operable to perform a data detection on the derivative of the decoded data set and to provide a second detected data set that is written to the unified memory buffer.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括第一检测器，第二检测器，解码器和统一存储器缓冲器的可变迭代数据处理系统。由执行数据检测的第一检测器接收输入数据集，并提供第一检测数据集。解码器接收第一检测数据集的导数，并执行产生解码数据集的解码操作。在一些情况下，第一检测数据集的导数是第一检测数据集的交错版本。解码的数据集被写入统一的存储缓冲器。第一解码数据集可从统一存储器缓冲器检索，并且其导数被提供给第二检测器。在一些情况下，解码的导数是解码数据集的解交织版本。第二检测器可操作以对解码数据集的导数执行数据检测，并提供写入统一存储器缓冲器的第二检测数据集。

37. 发明申请

US20100042897A1 SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS 有权
标题翻译：在错误修正解码器中选择加强和减弱检查节点信息
公开(公告)号：US20100042897A1
公开(公告)日：2010-02-18
申请号：US12538915
申请日：2009-08-11
申请人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
发明人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
IPC分类号： H03M13/05 , G06F11/07 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.
摘要翻译：在一个实施例中，LDPC解码器具有多个校验节点单元（CNU）和控制器。最初，CNU基于由控制器选择的初始偏移值生成校验节点消息。如果解码器收敛于陷阱集合，则控制器为不满意的校验节点（MSC）（其位置近似）和/或不满足的校验节点（USC）选择新的偏移值。特别地，选择偏移值，使得（i）相对于MSC的消息相对于将使用初始偏移值生成的消息减少和/或（ii）相对于USC的消息相对于将使用初始偏移值生成的消息。然后继续解码指定数量的迭代以打破陷阱集。在其他实施例中，控制器选择缩放因子，而不是或附加于偏移值。

38. 发明申请

US20060209977A1 Global minimum-based MLD demapping for soft-output MIMO detection 有权
标题翻译：用于软输出MIMO检测的全局最小化MLD解映射
公开(公告)号：US20060209977A1
公开(公告)日：2006-09-21
申请号：US11085026
申请日：2005-03-16
申请人： Nils Graef , Joachim Hammerschmidt
发明人： Nils Graef , Joachim Hammerschmidt
IPC分类号： H04L5/12
CPC分类号： H04L1/06 , H04L5/023
摘要： A method for generating soft bit values for a multi-bit symbol encoded in one or more received signals comprises (a) for a plurality of different combinations of multiple bit values, iteratively generating, for each combination, a metric value based on the one or more received signals. The method further comprises (b) for each iteration, maintaining (i) a global extremum register containing a global extremum of the metric values; (ii) a bit occupancy for the global extremum register; and (iii) a plurality of bit bk registers, one for each bit bk in the symbol. Each bit bk register contains an extremum of the metric values corresponding to combinations of multiple bit values whose bit bk value is opposite the bit bk value of the bit occupancy for the global extremum register. The method further comprises (c) generating, for each bit bk in the symbol, a soft bit value based on a difference between the value in the global extremum register and the value in the corresponding bit bk register.
摘要翻译：一种用于为在一个或多个接收信号中编码的多比特符号产生软比特值的方法包括（a）针对多个比特值的多个不同组合，对于每个组合迭代地生成基于该一个或多个更多的信号。该方法还包括（b）对于每次迭代，维持（i）包含度量值的全局极值的全局极值寄存器; （ii）全球极值登记册的位占有率; 和（iii）多个位b个k个寄存器，一个用于符号中的每个位b 。每个位b k k寄存器包含对应于其位b k k值与位b k k相反的多位值的组合的量度值的极值 >全局极值寄存器的位占用值。该方法还包括（c）针对符号中的每个比特b产生基于全局极值寄存器中的值与相应比特b < SUB> k 寄存器。

39. 发明申请

US20060195772A1 Method and apparatus for evaluating performance of a read channel 有权
标题翻译：用于评估读通道性能的方法和装置
公开(公告)号：US20060195772A1
公开(公告)日：2006-08-31
申请号：US11068224
申请日：2005-02-28
申请人： Nils Graef , Zachary Keirn
发明人： Nils Graef , Zachary Keirn
IPC分类号： H03M13/03
CPC分类号： H03M13/47 , H03M13/3905 , H03M13/4146 , H03M13/612
摘要： Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.
摘要翻译：提供了用于测量读取通道的性能的方法和装置。诸如SOVA和最大后验（MAP）检测器的多种检测技术产生与比特决定相关联的比特决策和相应的可靠性值。与比特决定相关联的可靠性值可以例如以对数似然比（LLR）的形式表示。可靠性值可以被监视并用作性能测量。本发明提供了通常与BER直接相关的信道性能测量，但可以在较少的时间内收集。

40. 发明授权

US09069687B2 Memory read-channel with selective transmission of error correction data 有权
标题翻译：存储器读通道，选择性地传输纠错数据
公开(公告)号：US09069687B2
公开(公告)日：2015-06-30
申请号：US12696572
申请日：2010-01-29
申请人： Nirav P. Dave , Nils Graef , Johnson Yen
发明人： Nirav P. Dave , Nils Graef , Johnson Yen
IPC分类号： H03M13/00 , G11C29/00 , G06F11/10 , H03M13/09 , H03M13/29 , H03M13/07 , H03M13/15
CPC分类号： G06F11/10 , H03M13/07 , H03M13/09 , H03M13/15 , H03M13/29
摘要： A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.
摘要翻译：存储器读通道被提供有错误校正数据的选择性传输。当不需要纠错码时，所公开的读通道提高了吞吐量并降低了功耗。从存储器件读取的数据包括用户数据，错误检测数据和纠错数据。在一个实施例中，评估错误检测数据以确定是否存在数据错误; 并且仅当检测到数据错误时才发送纠错数据。在另一个实施例中，在数据传输期间评估错误检测数据以确定是否存在数据错误，并且如果检测到数据错误则传输被暂停。通常，错误检测数据包括循环冗余校验，纠错数据包括奇偶校验数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式