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31. 发明授权

US07676603B2 Write combining protocol between processors and chipsets 失效
标题翻译：在处理器和芯片组之间写入组合协议
公开(公告)号：US07676603B2
公开(公告)日：2010-03-09
申请号：US10828872
申请日：2004-04-20
申请人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth C. Creta , Aaron T. Spink , Lance E. Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

32. 发明申请

US20080109565A1 PCI express enhancements and extensions 有权
标题翻译： PCI Express增强和扩展
公开(公告)号：US20080109565A1
公开(公告)日：2008-05-08
申请号：US11592341
申请日：2006-11-02
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Fallk , Avi Arraham Mendelson , Ilan Pardo , Eran Tamari , Ellezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Fallk , Avi Arraham Mendelson , Ilan Pardo , Eran Tamari , Ellezer Weissmann , Doron Shamia
IPC分类号： G06F3/01
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

33. 发明授权

US07152128B2 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US07152128B2
公开(公告)日：2006-12-19
申请号：US10227600
申请日：2002-08-23
申请人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，描述了一种方法，其包括从通过GIO链路耦合的远程GIO接口在一般输入/输出（GIO）接口处接收数据报，验证嵌入在所接收的数据报中的一个或多个分组的内容，以及向在将嵌入式数据包推送到GIO接口的事务层之前，数据报成功接收数据报的正确验证的远程GIO接口。还描述了其它实施例。

34. 发明授权

US06976115B2 Peer-to-peer bus segment bridging 有权
标题翻译：点对点公交线路桥接
公开(公告)号：US06976115B2
公开(公告)日：2005-12-13
申请号：US10112344
申请日：2002-03-28
申请人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
发明人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
IPC分类号： G06F3/00 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4031
摘要： A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
摘要翻译：描述了一种用于促进桥接总线段之间的对等通信的正确排序的方法和装置。根据本发明的一个实施例，当检测到连接在桥的同一侧上的分开的总线段上的设备之间的对等通信时，发出围栏命令。 fence命令插入到与总线段相对应的I / O集线器中的多个缓冲器中，以迫使临时排序I / O集线器的所有管道。一旦从该缓冲器读取了fence命令，则该中继器禁止处理来自缓冲器的后续命令，直到从多个缓冲器中的所有其他缓冲器读取相应的fence命令，从而确保对等通信的正确排序。

35. 发明授权

US06691192B2 Enhanced general input/output architecture and related methods for establishing virtual channels therein 有权
标题翻译：增强的一般输入/输出架构及其中建立虚拟通道的相关方法
公开(公告)号：US06691192B2
公开(公告)日：2004-02-10
申请号：US09968620
申请日：2001-09-30
申请人： Jasmin Ajanovic , David Harriman
发明人： Jasmin Ajanovic , David Harriman
IPC分类号： G06F1340
CPC分类号： G06F13/124
摘要： A point-to-point interconnection and communication architecture, protocol and related methods is presented.
摘要翻译：提出了一种点对点互连和通信架构，协议和相关方法。

36. 发明授权

US06370624B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06370624B1
公开(公告)日：2002-04-09
申请号：US09712010
申请日：2000-11-13
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

37. 发明授权

US06199145B1 Configurable page closing method and apparatus for multi-port host bridges 失效
标题翻译：用于多端口主机桥的可配置的页面关闭方法和装置
公开(公告)号：US06199145B1
公开(公告)日：2001-03-06
申请号：US09032434
申请日：1998-02-27
申请人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
发明人： Jasmin Ajanovic , Michael W. Williams , Robert N. Murdoch
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.
摘要翻译：一种用于多端口主机桥的页面关闭方法和装置。根据所公开的方法，从多个命令端口接收多个存储器访问命令。从命令端口之一中选择一个命令作为执行的下一个存储器访问命令。响应于作为下一个存储器访问命令选择的命令，多个页面的存储器被关闭。关闭的页数至少部分地由哪个命令端口提供下一个存储器访问命令确定。

38. 发明授权

US5666556A Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit 失效
标题翻译：用于重定向寄存器访问请求的方法和装置，其中寄存器集与中央处理单元分离
公开(公告)号：US5666556A
公开(公告)日：1997-09-09
申请号：US710572
申请日：1996-09-19
申请人： Narendra Khandekar , Jasmin Ajanovic
发明人： Narendra Khandekar , Jasmin Ajanovic
IPC分类号： G06F13/40 , G06F12/06
CPC分类号： G06F13/4027
摘要： A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.
摘要翻译：寄存器地址空间被定义为具有足够大的容量以容纳所需寄存器的数量的显着增长。未使用的寄存器位置保留供将来使用。指向保留地址的访问请求被重定向到物理寄存器，该物理寄存器包含与物理寄存器与访问最初指向的保留地址相关联时返回的相同存储值。物理寄存器与任何中央处理单元分开。

39. 发明申请

US20140129747A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
标题翻译：一般输入/输出结构，协议和相关方法实施流量控制
公开(公告)号：US20140129747A1
公开(公告)日：2014-05-08
申请号：US14145376
申请日：2013-12-31
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F13/42
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.
摘要翻译：提供一种存储装置，用于维持要通过要在数据链路上实现的信道上的事务相关联地授予设备的流量控制信用的计数，并且提供控制逻辑以向该设备传送数量的指示与数据链路的重置相关联的设备的流量控制信用。

40. 发明授权

US08566473B2 General input/output architecture, protocol and related methods to implement flow control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US08566473B2
公开(公告)日：2013-10-22
申请号：US12395497
申请日：2009-02-27
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，用于增强的一般输入/输出通信架构的方法包括：初始化虚拟通道初始化时初始化与虚拟通道相关联的通用输入/输出（GIO）接口内的流控制机制，以及在虚拟通道初始化时跟踪接收缓冲区可用性通过监视与从GIO接口发送到远程GIO接口的内容量相关联的指示，通过虚拟通道与远程GIO接口耦合到GIO接口。

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