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31. 发明授权

US06198128B1 Method of manufacturing a semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：US06198128B1
公开(公告)日：2001-03-06
申请号：US09390662
申请日：1999-09-07
申请人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
发明人： Hisao Asakura , Yoshitaka Tadaki , Toshihiro Sekiguchi , Ryo Nagai , Masafumi Miyamoto , Masayuki Nakamura , Shinichi Miyatake , Tsuyuki Suzuki , Masahiro Hyoma
IPC分类号： H01L2972
CPC分类号： H01L29/66537 , H01L21/26586 , H01L21/823814
摘要： In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.
摘要翻译：在用于抑制MISFET的短沟道效应的杂质与其主表面倾斜地引入半导体衬底的情况下，彼此相邻的栅电极被布置成使得沿与栅电极交叉的方向引入的杂质不会被引入位于栅电极之间的半导体衬底的部分中，并且MISFET的源极区域被布置在栅电极之间的部分中。

32. 发明授权

US5937290A Method of manufacturing semiconductor integrated circuit devices using phase shifting mask 失效
标题翻译：使用相移掩模制造半导体集成电路器件的方法
公开(公告)号：US5937290A
公开(公告)日：1999-08-10
申请号：US862992
申请日：1997-05-27
申请人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
发明人： Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Katsuo Yuhara , Kazuhiko Saito , Shinya Nishio , Michio Tanaka , Michio Nishimura , Toshiyuki Kaeriyama , Songsu Cho
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , Y10S438/942
摘要： In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.
摘要翻译：在根据本发明的制造半导体集成电路器件的方法的实施例中，字线被提供成直线形式，其用作两个选择MOSFET的栅电极，所述选择MOSFET形成为由LOCOS包围的有源区域的中心部分对称地形成半导体衬底上的氧化膜，位线具有直段和突出段。每个突出部分形成为从位线突出，并且通过第一接触孔连接到形成在有源区域的中心部分处的第一半导体区域。直线段和突出段通过两个单独的曝光步骤分别形成。

33. 发明授权

US5629898A Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device 失效
标题翻译：动态存储器件，存储器模块和刷新动态存储器件的方法
公开(公告)号：US5629898A
公开(公告)日：1997-05-13
申请号：US607977
申请日：1996-02-29
申请人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
发明人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4061
摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
摘要翻译：对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。从刷新地址计数器输出的进位信号由分频器分频。对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中。根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效。

34. 发明授权

US5578849A Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance 失效
标题翻译：半导体集成电路器件包括具有增加的信息存储电容的存储单元的存储器件
公开(公告)号：US5578849A
公开(公告)日：1996-11-26
申请号：US341966
申请日：1994-11-16
申请人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
发明人： Yoshitaka Tadaki , Jun Murata , Toshihiro Sekiguchi , Hideo Aoki , Keizo Kawakita , Hiroyuki Uchiyama , Michio Nishimura , Michio Tanaka , Yuji Ezaki , Kazuhiko Saitoh , Katsuo Yuhara , Songsu Cho
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L2924/0002
摘要： A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.
摘要翻译：存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。每个存储单元具有开关晶体管和信息存储电容器。每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域信息存储电容器。形成在一个位线导体下方的一系列存储单元对单元结构分别相对于位于一个位线导体的相对侧上相邻的第一和第二位线导体下方的一系列存储单元对单元结构位移地移位，形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接形成在一个位线导体下的存储单元对单元结构的导体。

35. 发明授权

US5504029A Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
标题翻译：具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法
公开(公告)号：US5504029A
公开(公告)日：1996-04-02
申请号：US254562
申请日：1994-06-06
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。电容器元件的电介质膜与其上的电容器电极层共同扩展。电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

36. 发明授权

US08294225B2 Ultrasonic transducer and manufacturing method 有权
标题翻译：超声波换能器及制造方法
公开(公告)号：US08294225B2
公开(公告)日：2012-10-23
申请号：US12407414
申请日：2009-03-19
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
IPC分类号： H01L21/00
CPC分类号： B06B1/0292 , Y10T29/49005
摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.
摘要翻译：本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。在包括多个下电极的超声波换能器中，覆盖下电极的绝缘膜，形成为与绝缘膜上的下电极重叠的多个中空部，填充中空部之间的间隙的绝缘膜，覆盖中空部的绝缘膜，绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连，中空部分和绝缘膜的表面被平坦化到相同的高度。

37. 发明授权

US07512038B2 Ultrasonic transducer and manufacturing method 有权
标题翻译：超声波换能器及制造方法
公开(公告)号：US07512038B2
公开(公告)日：2009-03-31
申请号：US11671040
申请日：2007-02-05
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki
IPC分类号： H04R19/00
CPC分类号： B06B1/0292 , Y10T29/49005
摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, —an insulation film covering the lower electrodes, —plural hollow parts formed to overlap the lower electrodes on the insulation film, —an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, —the surfaces of the hollow parts and insulation film are flattened to the same height.
摘要翻译：本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。在包括多个下电极的超声波换能器中， - 覆盖下电极的绝缘膜， - 形成为与绝缘膜上的下电极重叠的 - 中空部分， - 填充中空部分之间的间隙的绝缘膜，覆盖中空部分和绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连， - 中空部分和绝缘膜的表面被平坦化到相同的高度。

38. 发明申请

US20070052093A1 Ultrasonic transducer and manufacturing method thereof 有权
标题翻译：超声波换能器及其制造方法
公开(公告)号：US20070052093A1
公开(公告)日：2007-03-08
申请号：US11489612
申请日：2006-07-20
申请人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki , Tatsuya Nagata
发明人： Shuntaro Machida , Hiroyuki Enomoto , Yoshitaka Tadaki , Tatsuya Nagata
IPC分类号： H01L23/48
CPC分类号： B06B1/0292
摘要： Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.
摘要翻译：公开了一种超声换能器的改进结构，其中即使膜的底部与下电极接触，电荷也不容易注入到绝缘膜中，并且其制造方法不使用晶片层压技术。超声波换能器包括下电极; 形成在所述第一电极上的空腔层; 覆盖空腔层的绝缘膜; 以及形成在绝缘膜上的上电极，其中，所述空腔层包括形成为从所述空腔层突出的绝缘膜的突起。此外，在上部电极中形成开口，并且其上形成有开口的该上部电极沉积在从顶部观察时不与绝缘膜的突起重叠的位置。

39. 发明授权

US06649956B2 Semiconductor integrated circuit device and manufacturing method thereof 有权
公开(公告)号：US06649956B2
公开(公告)日：2003-11-18
申请号：US10227799
申请日：2002-08-27
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

40. 发明授权

US06483136B1 Semiconductor integrated circuit and method of fabricating the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06483136B1
公开(公告)日：2002-11-19
申请号：US09446302
申请日：2000-04-14
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.
摘要翻译：在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案，在半导体衬底（1）的一个主表面上沿X方向线性地延伸。存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度，栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

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