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31. 发明专利

JPH03129765A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03129765A
公开(公告)日：1991-06-03
申请号：JP12219990
申请日：1990-05-11
申请人： NIPPON DENSO CO
发明人： SAKAKIBARA TOSHIO , YAMAOKA MASAMI
IPC分类号： H01L21/18 , H01L21/20 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/786
摘要： PURPOSE:To suppress the level difference, even in case of island isolation, by providing a semiconductor region having a specified thickness and a specified conductivity where the concentration of impurities lowers gradually from the surface toward the bottom face. CONSTITUTION:Wafers are stuck together by adhering oxide films 2, 5 each other, and then the other main face of a first single crystal silicon substrate 1 is polished so that the first single crystal silicon substrate 1 has a thickness thinner than 6mum, e.g. in the range of 1.5-2.5mum. The first single crystal silicon substrate 1 is then selectively etched to form island regions 6, 7 corresponding to the semiconductor region. A gate oxide film 10 is formed in the DMOS forming region and on the surface of the island regions 6, 7. P-type impurities, e.g. B(boron), are then ion implanted to form a P -type region 9 on the surface section of the island region 6. The impurities are dispersed upto the bottom face of the island region contacting with the oxide film 2. Since the impurities are dispersed in the island region 6, the impurities concentration lowers gradually from the surface toward the bottom face of the island region 6.

32. 发明专利

JPH0379035A MOS TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0379035A
公开(公告)日：1991-04-04
申请号：JP21678389
申请日：1989-08-22
申请人： NIPPON DENSO CO
发明人： SAKAKIBARA TOSHIO , YAMAOKA MASAMI
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78 , H01L29/786
摘要： PURPOSE:To obtain an inexpensive semiconductor layer with improved crystal and restrict kink phenomena by forming a diffusion layer with a higher impurity concentration near a drain region than that of a semiconductor layer and by biasing a substrate through the diffusion layer. CONSTITUTION:A diffusion layer 11 with a higher impurity concentration than that of a semiconductor layer is formed near a drain region 10 and a substrate is biased through the diffusion layer. For example, an electrode material for biasing source/substrate 13 which is grounded through a contact hole 12 is placed and a drain electrode material 15 where a positive voltage is applied to through a contact hole 14 is placed. Also, a positive voltage is applied to a polysilicon film 5a which becomes a gate electrode, thus obtaining an inexpensive semiconductor layer with improved crystal and restricting kink phenomena.

33. 发明专利

JPH01122169A SEMICONDUCTOR DEVICE FOR POWER 失效
公开(公告)号：JPH01122169A
公开(公告)日：1989-05-15
申请号：JP27935887
申请日：1987-11-06
申请人： NIPPON DENSO CO
发明人： FUJIMOTO YUTAKA , YAMAOKA MASAMI , TSUZUKI YUKIO
IPC分类号： H01L21/8236 , H01L27/088 , H01L29/78
摘要： PURPOSE:To simplify a structure and a manufacturing process by forming a P- or N-type well to a semiconductor substrate, and composing control elements of enhancement type and depletion type MOSFET only of an N channel or a P channel shaped to the well. CONSTITUTION:A control region 14 is set in response to a P well 15 formed in response to the surface section of a semiconductor substrate 11, and N channel MOSFEETs 16, 17 are shaped to the P well 15. In this case, the MOSFET 16 is constituted to be an enhancement type while the MOSFET 17 is constituted to be a depletion type by driving N ions 18 by using a mask. Consequently, a manufacturing process is not complicated particularly and control elements can be incorporated and set to the same semiconductor chip together with active elements according to simplified element structure.

34. 发明专利

JPS63308387A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63308387A
公开(公告)日：1988-12-15
申请号：JP14424587
申请日：1987-06-10
申请人： NIPPON DENSO CO
发明人： TSUZUKI YUKIO , YAMAOKA MASAMI
IPC分类号： H01L21/336 , H01L29/10 , H01L29/45 , H01L29/78
摘要： PURPOSE:To enable the unit size to be miniaturized by a method wherein a conductive channel is formed in a selfalignment manner using the second insulating layer and sidewalls as masks. CONSTITUTION:During the process of forming an N type diffused region 8 in a P type well region 7, the surface of the N type diffused region 8 need not be formed into square shape to be formed on overall surface in a region encircled by an insulating film 5 so that a resist may not be selectively formed by photoetching process. Furthermore, during the process of forming a recession 10, the recession 10 is formed by RIE in a selfalignment manner using sidewalls 9a and the insulating film 5 as masks and electrically connected to the P type well region 7 and the N type diffused region 8 by forming an Al wiring 11 in the recession 10. Through these procedures, the allowance for the position slip made during the photoetching process can be made needless enabling the unit cell size to be miniaturized.

35. 发明专利

JPS63234166A CURRENT DETECTOR 失效
公开(公告)号：JPS63234166A
公开(公告)日：1988-09-29
申请号：JP6861187
申请日：1987-03-23
申请人： NIPPON DENSO CO
发明人： FURUTA SHIGEKI , YAMAOKA MASAMI
IPC分类号： G05F1/10 , B60Q11/00 , G01R19/00 , G01R19/165
摘要： PURPOSE:To accurately detect current by forming one of a couple of resistances by using a material which has negative resistance temperature characteristics, varying the resistance value of one resistance according to negative resistance characteristics even if the temperature of the other varies, and maintaining a detected voltage at a proper value. CONSTITUTION:This detector consists of flash lamps 10a-10f, an oscillation control circuit 20, a changeover switch 30, and a semiconductor chip E. Further, the device is formed of the chip E, a longitudinal power MOSFET 40, and a voltage dividing circuit 50, and boron, etc., is implanted in polycrystalline silicon to give one resistance 51 of the circuit 50 the negative resistance temperature characteristics. Consequently, even if the breaking of a wire occurs to the lamp 10a, etc. when the temperature of the CHIP E is high, variations in resistance values of the resistances 51 and 52 cancel each other and a detection voltage from the circuit 50 has no error. Therefore, the state of a load current is accurately detected from the detection voltage.

36. 发明专利

JPS57117275A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS57117275A
公开(公告)日：1982-07-21
申请号：JP353581
申请日：1981-01-12
申请人： Nippon Denso Co Ltd
发明人： YAMAOKA MASAMI
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L29/417 , H01L29/72 , H01L29/73
CPC分类号： H01L29/72
摘要： PURPOSE:To prevent the destruction of a semiconductor device to be caused by overvoltage by a method wherein a diode region having shallow diffusion depth is formed surrounding a base region formed by diffusion from the main surface of a collector substrate. CONSTITUTION:A P type base region 3 is formed by diffusion from the main surface of an N type collector substrate 1. Duffusion is performed from the main surface thereof to form a diode region 5 of which one side is formed as to surround the base region 3 and the other side as to exist in the collector substrate 1. At this time, depth of diffusion of the diode region 5 is made shallower than the base region 3. Accordingly the same result can be obtained with the case when a protective diode is connected to a transistor by outside equipment, VCE of the transistor is limited by breakdown voltage of the diode, and withstand voltage of the transistor is enhanced.
摘要翻译：目的：为了防止半导体器件由于过电压的破坏，其中通过从集电器基板的主表面扩散形成的基极区域形成具有浅扩散深度的二极管区域的方法。构成：AP型基区3由N型集电板1的主表面扩散形成。从其主表面进行扩散，形成二极管区5，二极管区5的一侧形成为包围基极区域3和另一侧存在于集电体衬底1中。此时，使二极管区域5的扩散深度比基极区域3浅。因此，在保护性的情况下，可以获得相同的结果二极管由外部设备连接到晶体管，晶体管的VCE受二极管的击穿电压的限制，晶体管的耐压提高。

37. 发明专利

JP2522208B2 失效
公开(公告)号：JP2522208B2
公开(公告)日：1996-08-07
申请号：JP6265287
申请日：1987-03-19
申请人： NIPPON DENSO CO
发明人： TSUZUKI YUKIO , YAMAOKA MASAMI
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L29/78 , H02H9/02 , H03F1/42 , H03F1/52

38. 发明专利

JPH0750303A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0750303A
公开(公告)日：1995-02-21
申请号：JP7730394
申请日：1994-04-15
申请人： NIPPON DENSO CO
发明人： TSUZUKI YUKIO , YAMAOKA MASAMI , MUTO KOJI
IPC分类号： H01L21/265 , H01L21/324 , H01L21/329 , H01L29/861
摘要： PURPOSE:To utilize the merit of the structure of a polycrystalline silicon layer, and provide a semiconductor device whose breakdown strength is improved. CONSTITUTION:On the main surface of a semiconductor substrate 1, an insulating film 2 is formed, a polycrystalline silicon island 3 is formed, and a thermal oxide film 5 is formed. Polycrystalline silicon is annealed at a high temperature. When the temperature is higher than or equal to 1100 deg.C, and the annealing time 18 longer than or equal to 15 minutes, unpaired electron density can be made small, and fine defects can be reduced, so that polycrystalline silicon of high quality can be obtained. A P region 3a and an N region 3b are formed, and electrodes are formed in a specified region, thereby forming a polycrystalline silicon diode.

39. 发明专利

JPH03108766A HIGH BREAKDOWN STRENGTH TRANSISTOR 失效
公开(公告)号：JPH03108766A
公开(公告)日：1991-05-08
申请号：JP24737289
申请日：1989-09-22
申请人： NIPPON DENSO CO
发明人： MUTO KOJI , YAMAOKA MASAMI
IPC分类号： H01L29/78 , H01L29/786
摘要： PURPOSE:To obtain a transistor in which high breakdown strength is provided while employing conventional manufacturing steps as they are by insulation- isolating a plurality of MOS transistors by insulated main surface and a substrate and an insulating film, commonly connecting the gates of the transistors, and sequentially connecting drains and sources in series. CONSTITUTION:A substrate 1 in which at least part of its main surface is electrically insulated, a plurality of MOS field effect transistors Tr1, Tr2 formed on the insulated main surface of the substrate 1, and insulating films 14, 24, 71 for electrically insulating the transistors Tr1, Tr2 are provided, gates 15, 25 of the transistors Tr1, Tr2 are commonly connected, the source 13 of the one transistor Tr1 is sequentially connected to the drain 21 of the other transistor Tr2 between the transistors Tr1 and Tr2, and the transistors Tr1, Tr2 are connected in series as one transistor.

40. 发明专利

JPH02285679A SEMICONDUCTOR DEVICE FOR POWER USE 失效
公开(公告)号：JPH02285679A
公开(公告)日：1990-11-22
申请号：JP10655389
申请日：1989-04-26
申请人： NIPPON DENSO CO
发明人： TSUZUKI YASUAKI , TSUZUKI YUKIO , SUZUKI TOSHIO , FUJIMOTO YUTAKA , YAMAOKA MASAMI
IPC分类号： H01L29/78 , H01L21/76 , H01L27/04
摘要： PURPOSE:To make it possible to avoid an adverse effect due to a parasitic transistor and to obtain a highly reliable semiconductor element for power use by a method wherein an insulating film of a film thickness thikcer than that of a gate insulating film in each active region cell is formed between a main current part and an emulation current part. CONSTITUTION:A plurality of active region cells are formed by insulated-gate type transistor cells (MOS transistor cells) 12 to 14, at least one of the active region cells is used as a main current part (a) and at the same time, another one of the active region cells is used as an emulation current part (b), a common drain electrode 22, which comes into contact to the main and emulation current parts (a) and (b), is formed and at the same time, individual source electrodes (a main current part source electrode and an emulation current part source electrode) 23 and 24, which respectively come into contact to the main and emulation current parts (a) and (b), are formed. In such a semiconductor element for power use, an insulating film 26 of a film thickness thicker than that of a gate insulating film 20 in each active region cell is formed between the above main and emulation current parts. Thereby, a parasitic transistor is prevented from being turned-ON and the erroneous operation of the element and a reduction in an element current level detection accuracy can be prevented.

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