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31. 发明申请

US20140047199A1 Memory-Link Compression for Graphic Processor Unit 有权
标题翻译：图形处理器单元的内存链接压缩
公开(公告)号：US20140047199A1
公开(公告)日：2014-02-13
申请号：US13569999
申请日：2012-08-08
申请人： Nam Sung Kim
发明人： Nam Sung Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F12/08 , H04N19/176
摘要： A graphic processing unit having multiple computational elements flexibly interconnected to memory elements provides for data compressors/decompressors in the memory channels communicating between the computational elements and memory elements to provide an effective increase in bandwidth of those connections by the compression of data transferred thereon.
摘要翻译：具有与存储器元件灵活互连的多个计算元件的图形处理单元提供在计算元件和存储元件之间通信的存储器通道中的数据压缩器/解压缩器，以通过压缩其上传送的数据来提供这些连接的带宽的有效增加。

32. 发明申请

US20130094318A1 Energy Efficient Processor Having Heterogeneous Cache 有权
标题翻译：具有异构缓存的节能处理器
公开(公告)号：US20130094318A1
公开(公告)日：2013-04-18
申请号：US13271771
申请日：2011-10-12
申请人： Nam Sung Kim , Stark C. Draper
发明人： Nam Sung Kim , Stark C. Draper
IPC分类号： G11C5/14
CPC分类号： G06F12/0864 , G06F11/1064 , G06F2212/1028 , Y02D10/13
摘要： A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
摘要翻译：异构缓存结构提供多个不同方式的多个存储器单元，每个存储单元与不同的最小电压相关联，低于该最小电压时，存储器单元产生实质的状态误差。缓存的降压操作可伴随着根据电压降低而不同的方式停用。存储器单元之间的区别可以通过将不同量的集成电路区域投入到每个存储器单元来实现，方法是通过改变包括存储器单元的晶体管的尺寸或者以共享误差的形式将额外的晶体管用于每个存储器单元更正代码或备份存储单元。

33. 发明授权

US08298897B2 Asymmetric channel MOSFET 失效
公开(公告)号：US08298897B2
公开(公告)日：2012-10-30
申请号：US13428061
申请日：2012-03-23
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.

34. 发明申请

US20120042176A1 Method and Apparatus for Optimizing Clock Speed and Power Dissipation in Multicore Architectures 有权
标题翻译：在多核架构中优化时钟速度和功耗的方法和装置
公开(公告)号：US20120042176A1
公开(公告)日：2012-02-16
申请号：US12857167
申请日：2010-08-16
申请人： Nam Sung Kim
发明人： Nam Sung Kim
IPC分类号： G06F1/26 , G06F1/32 , G06F1/12
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A multicore processor provides for local power control at each of the cores which is used to lower the maximum operating frequency of cores by any amount above of the maximum operating frequency of the slowest core. This power savings is then used to increase the maximum operating frequency of the frequency balanced cores within a power constraint.
摘要翻译：多核处理器提供每个核心处的局部功率控制，用于将核心的最大工作频率降低到最高核心的最大工作频率以上的任何量级。然后，这种功率节省用于在功率约束内增加频率平衡核心的最大工作频率。

35. 发明授权

US07812631B2 Sleep transistor array apparatus and method with leakage control circuitry 有权
标题翻译：具有泄漏控制电路的睡眠晶体管阵列设备和方法
公开(公告)号：US07812631B2
公开(公告)日：2010-10-12
申请号：US11609823
申请日：2006-12-12
申请人： Nam Sung Kim , Vivek De
发明人： Nam Sung Kim , Vivek De
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0016
摘要： In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.
摘要翻译：在一些实施例中，提供了一种睡眠晶体管阵列，其中可以在有源模式期间启用所述晶体管的组合以根据芯片或相关芯片的泄漏特性来减少泄漏。

36. 发明申请

US20080307277A1 DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING 有权
标题翻译：延迟故障检测使用锁定与错误采样
公开(公告)号：US20080307277A1
公开(公告)日：2008-12-11
申请号：US11758124
申请日：2007-06-05
申请人： James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
发明人： James W. Tschanz , Keith A. Bowman , Nam Sung Kim , Chris Wilkerson , Shih-Lien L. Lu , Tanay Karnik
IPC分类号： G06F11/25
CPC分类号： G06F11/24
摘要： Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
摘要翻译：一些实施例使用锁存器提供从路径级输出的数据信号的采样，使用边沿触发的触发器对从路径级输出的数据信号进行采样，将由锁存器输出的第一值与由边沿触发触发器，并且如果第一值不同于第二值，则产生误差信号。

37. 发明授权

US09690350B2 Method and apparatus for power reduction during lane divergence 有权
公开(公告)号：US09690350B2
公开(公告)日：2017-06-27
申请号：US13605460
申请日：2012-09-06
申请人： Nam Sung Kim , James M. O'Connor , Michael J. Schulte , Vijay Janapa Reddi
发明人： Nam Sung Kim , James M. O'Connor , Michael J. Schulte , Vijay Janapa Reddi
IPC分类号： G06F1/00 , G06F1/32 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30083 , G06F9/3851 , G06F9/3887 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.

38. 发明授权

US08687453B2 Energy efficient processor having heterogeneous cache 有权
标题翻译：具有异构缓存的节能处理器
公开(公告)号：US08687453B2
公开(公告)日：2014-04-01
申请号：US13271771
申请日：2011-10-12
申请人： Nam Sung Kim , Stark C. Draper
发明人： Nam Sung Kim , Stark C. Draper
IPC分类号： G11C5/14
CPC分类号： G06F12/0864 , G06F11/1064 , G06F2212/1028 , Y02D10/13
摘要： A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
摘要翻译：异构缓存结构提供多个不同方式的多个存储器单元，每个存储单元与不同的最小电压相关联，低于该最小电压时，存储器单元缓存的降压操作可伴随着根据电压降低而不同的方式停用。存储器单元之间的区别可以通过将不同量的集成电路区域投入到每个存储器单元来实现，方法是通过改变包括存储器单元的晶体管的尺寸或者以共享误差的形式将额外的晶体管用于每个存储器单元更正代码或备份存储单元。

39. 发明申请

US20120242392A1 Leakage Power Management Using Programmable Power Gating Transistors and On-Chip Aging and Temperature Tracking Circuit 有权
标题翻译：使用可编程电源门控晶体管和片上老化和温度跟踪电路进行泄漏电源管理
公开(公告)号：US20120242392A1
公开(公告)日：2012-09-27
申请号：US13053374
申请日：2011-03-22
申请人： Nam Sung Kim
发明人： Nam Sung Kim
IPC分类号： H03K17/14 , H03K17/56
CPC分类号： H03K19/0016
摘要： The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.
摘要翻译：在休眠模式下用于功率降低的集成电路上的功率门控晶体管的数量在唤醒状态期间被控制，以调节电流流动，并因此调节功率门控晶体管上的电压降，这是这些晶体管的老化和/ 或集成电路的温度的函数。以这种方式，集成电路的电源电压可以被更好地定制，以在集成电路较小或在低温下工作时最小化电流泄漏。

40. 发明授权

US08237197B2 Asymmetric channel MOSFET 失效
标题翻译：非对称沟道MOSFET
公开(公告)号：US08237197B2
公开(公告)日：2012-08-07
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

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