会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 31. 发明授权
    • Information processing system
    • 信息处理系统
    • US08601277B2
    • 2013-12-03
    • US10515936
    • 2003-05-29
    • Akiko AsamiTakashi SuzukiTakashi Takeda
    • Akiko AsamiTakashi SuzukiTakashi Takeda
    • H04L29/06
    • G06K7/10366A63H3/36G06F21/34G06K19/0772G06Q10/10G06Q20/04G06Q20/12G06Q20/28G06Q20/341G06Q20/3433G06Q20/40145G06Q30/06G07F7/02G07F7/08G07F7/1008G07F7/122H04L63/0853H04W4/00H04W8/26
    • An information processing system, an information processing method for use with the system, an information providing system, and information providing method for use with the system, an information processing apparatus, an information processing method for use with the apparatus, a doll, an object, a program storage medium, and a program for authenticating users reliably are provided. A user acquires beforehand a doll called Pochara the Good Friend incorporating an IC chip that stores a user ID for authenticating the user. When the user mounts the doll on a platform 23 connected to a personal computer 22, the user ID is read from the IC chip by a reader housed in the platform 23 and transmitted over the Internet 1 to a Pochara service server 9. The server 9 has a Pochara database 10 holding personal information about users of the service. The transmitted user ID is checked against the personal information in the database for authentication. This invention applies advantageously to servers offering services through networks.
    • 信息处理系统,与系统一起使用的信息处理方法,信息提供系统以及与该系统一起使用的信息提供方法,信息处理装置,与该装置一起使用的信息处理方法,玩偶,物体 ,程序存储介质和用于可靠地认证用户的程序。 用户预先获取一种称为Pochara the Good Friend的娃娃,其中包含存储用于认证用户的用户ID的IC芯片。 当用户将娃娃安装在连接到个人计算机22的平台23上时,通过容纳在平台23中的读取器从IC芯片读取用户ID,并通过因特网1发送到Pochara服务服务器9.服务器9 具有Pochara数据库10,其中持有有关该服务用户的个人信息。 根据数据库中的个人信息检查发送的用户ID以进行认证。 本发明有利地适用于通过网络提供服务的服务器。
    • 32. 发明授权
    • Range sensor and range image sensor
    • 量程传感器和量程图像传感器
    • US08598674B2
    • 2013-12-03
    • US13498202
    • 2010-11-18
    • Mitsuhito MaseTakashi SuzukiTomohiro Yamazaki
    • Mitsuhito MaseTakashi SuzukiTomohiro Yamazaki
    • H01L27/146G01C3/08
    • H01L27/14643G01S7/4814G01S7/4816G01S7/4863G01S17/89H01L27/14603H01L27/1464
    • A range image sensor 1 is provided with a semiconductor substrate 1A having a light incident surface 1BK and a surface 1FT opposite to the light incident surface 1BK, a photogate electrode PG, first and second gate electrodes TX1, TX2, first and second semiconductor regions FD1, FD2, and a third semiconductor region SR1. The photogate electrode PG is provided on the surface 1FT. The first and second gate electrodes TX1, TX2 are provided next to the photogate electrode PG The first and second semiconductor regions FD1, FD2 accumulate respective charges flowing into regions immediately below the respective gate electrodes TX1, TX2. The third semiconductor region SR1 is located away from the first and second semiconductor regions FD1, FD2 and on the light incident surface 1BK side and has the conductivity type opposite to that of the first and second semiconductor regions FD1, FD2.
    • 范围图像传感器1设置有具有光入射表面1BK和与光入射表面1BK相对的表面1FT的半导体衬底1A,光栅电极PG,第一和第二栅电极TX1,TX2,第一和第二半导体区域FD1 ,FD2和第三半导体区域SR1。 光栅电极PG设置在表面1FT上。 第一和第二栅电极TX1,TX2设置在光栅电极PG的旁边。第一和第二半导体区域FD1,FD2累积流入各栅极电极TX1,TX2正下方的各个电荷。 第三半导体区域SR1远离第一和第二半导体区域FD1,FD2以及光入射面1BK侧,并且具有与第一和第二半导体区域FD1,FD2相反的导电类型。
    • 33. 发明授权
    • Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit
    • 在提交堆栈输入单元中登记的线程间负载仲裁控制检测信息和控制指令输入控制单元
    • US08561079B2
    • 2013-10-15
    • US12635801
    • 2009-12-11
    • Takashi SuzukiToshio Yoshida
    • Takashi SuzukiToshio Yoshida
    • G06F9/46G06F15/00
    • G06F9/3851
    • The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.
    • 同时多线程系统中的信息处理装置以线程间性能负载仲裁控制方式进行操作,包括:指令输入控制单元,用于在线程之间共享输入用于获取指令的算术单元中的指令的控制 存储器并基于该指令执行操作; 为每个线程提供的用于保存通过解码指令而获得的信息的提交栈条目; 指令完成顺序控制单元,用于根据从指令输入控制单元输入的指令的顺序,根据运算单元获得的运算结果来更新存储器和通用寄存器; 以及性能负载平衡分析单元,用于检测在提交堆栈条目中登记的信息并控制指令输入控制单元。