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31. 发明申请

US20110320881A1 ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM 有权
标题翻译：在传输介质中分离故障链路
公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译：隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个传输链路。在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

32. 发明申请

US20110138104A1 MULTI-WRITE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的多写编码
公开(公告)号：US20110138104A1
公开(公告)日：2011-06-09
申请号：US12631470
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/401 , G11C11/5621 , G11C16/3418 , G11C16/349
摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
摘要翻译：包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。存储器页面处于擦除状态或先前写入的状态。如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

33. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

34. 发明申请

US20140006897A1 CORRECTION OF STRUCTURED BURST ERRORS IN DATA 审中-公开
标题翻译：数据中结构化爆发误差的校正
公开(公告)号：US20140006897A1
公开(公告)日：2014-01-02
申请号：US13538214
申请日：2012-06-29
申请人： Michele M. Franceschini , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/15 , H03M13/152 , H03M13/17 , H03M13/2906 , H04L1/0045
摘要： Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.
摘要翻译：数据中的结构化突发错误的校正由包括编码器并且被配置为执行方法的系统提供。该方法包括接收包括多个数据子集的数据。数据由编码器使用第一纠错码和第二纠错码的组合进行编码。第一纠错码被配置为从数据子集之一中的结构化突发错误提供错误恢复，结构化突发错误的长度小于指定的最大长度。第二纠错码被配置为扩展第一纠错码，以便在数据子集中的结构化突发错误中提供错误恢复。输出编码数据。

35. 发明申请

US20130212427A1 RECLAIMING DISCARDED SOLID STATE DEVICES 有权
标题翻译：重新抛弃固定状态装置
公开(公告)号：US20130212427A1
公开(公告)日：2013-08-15
申请号：US13396020
申请日：2012-02-14
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/16
CPC分类号： G11C29/56008 , G06F11/2289 , G06F11/3409 , G11C16/349
摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.
摘要翻译：废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。因此可以减少由于废弃的存储器件造成的浪费。

36. 发明授权

US08472224B2 Adjustable write bins for multi-level analog memories 失效
标题翻译：适用于多级模拟存储器的可调式写入箱
公开(公告)号：US08472224B2
公开(公告)日：2013-06-25
申请号：US13355833
申请日：2012-01-23
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
摘要翻译：通过接收在能够存储一定范围的值的模拟存储器上执行写入的目标成本来选择存储器中的存储器。确定可能在值范围内创建的可能的仓和与每个可能仓相关联的成本。每个可能的仓包括一个或多个值。识别出一组垃圾箱，这些垃圾箱是可能的垃圾箱，其相关成本在目标成本的阈值之内。从具有非重叠值的分组组中选择最大数量的分区。所选择的存储槽与用于对模拟存储器的内容进行编码和解码的所选择的存储器的值一起存储。

37. 发明授权

US08464137B2 Probabilistic multi-tier error correction in not-and (NAND) flash memory 有权
标题翻译：不和（NAND）闪存中的概率多层纠错
公开(公告)号：US08464137B2
公开(公告)日：2013-06-11
申请号：US12960004
申请日：2010-12-03
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F11/00
CPC分类号： G06F11/1012 , H03M13/2906 , H03M13/3715 , H03M13/3738
摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.
摘要翻译：在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。该系统包括与存储器通信的解码器。解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。响应于接收到包含码字的页面之前写入的数据和存储器中其他页面的内容，生成第二层校验符号。响应于第二层校验符号校正码字。校正的码字被输出。

38. 发明授权

US08176234B2 Multi-write coding of non-volatile memories 有权
标题翻译：非易失性存储器的多写编码
公开(公告)号：US08176234B2
公开(公告)日：2012-05-08
申请号：US12631470
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/401 , G11C11/5621 , G11C16/3418 , G11C16/349
摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
摘要翻译：包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。存储器页面处于擦除状态或先前写入的状态。如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

39. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

40. 发明申请

US20110246703A1 CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US20110246703A1
公开(公告)日：2011-10-06
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

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