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31. 发明授权

US06744684B2 Semiconductor memory device with simple refresh control 有权
公开(公告)号：US06744684B2
公开(公告)日：2004-06-01
申请号：US09777694
申请日：2001-02-07
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C2207/104
摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

32. 发明授权

US06590511B2 Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve 失效
公开(公告)号：US06590511B2
公开(公告)日：2003-07-08
申请号：US09775711
申请日：2001-02-05
申请人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
发明人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
IPC分类号： H03M700
CPC分类号： H03M7/3084 , G11C15/00 , G11C15/04
摘要： A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

33. 发明授权

US06483139B1 Semiconductor memory device formed on semiconductor substrate 有权
标题翻译：形成在半导体衬底上的半导体存储器件
公开(公告)号：US06483139B1
公开(公告)日：2002-11-19
申请号：US09983294
申请日：2001-10-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L2976
CPC分类号： G11C11/4085 , G11C11/4076 , G11C2207/2281 , H01L27/10805
摘要： In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.
摘要翻译：在包含在系统LSI的存储电路部分的存储单元中，N沟道MOS晶体管的栅电极和电容器的单元板电极由相同的互连层形成。因此，可以仅使用CMOS逻辑处理来制造系统LSI，从而可以以低成本制造包括具有相对大容量的存储器电路部分的系统LSI。

34. 发明授权

US06459113B1 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells 失效
标题翻译：半导体集成电路器件及其制造方法，以及DRAM存储单元的单元尺寸计算方法
公开(公告)号：US06459113B1
公开(公告)日：2002-10-01
申请号：US09760804
申请日：2001-01-17
申请人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
IPC分类号： H01L27108
CPC分类号： H01L27/10805 , H01L27/0207
摘要： There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.
摘要翻译：提供了一种半导体集成电路器件，包括：场放置，通过在第一导电型半导体衬底上的最密堆积产生阵列形式的场图案，场图案包括限定有源区域的多个存储单元和器件隔离区域，并且分别以纵向和横向方向以预定间距布置，每个存储单元具有一定长度至宽度尺寸的图案; 在通过杂质注入形成的第二电导型扩散区域与有源区域之间提供电容器结构的单元板布置和通过电容器电介质以预定的单元板图案覆盖部分有源区域形成的单元板电极，细胞板图案以一定的长度尺寸在横向上延伸; 以及字线图案，其中在没有形成单元板电极的有源区域的空白区域的横向上布置字线图案，并且用作有源区域上的场效应晶体管的栅电极，所述字线图案是以预定间隔通过栅极氧化物形成的，其中所述存储单元的单元阵列的布局由最接近的封装单元配置提供。

35. 发明授权

US06452859B1 Dynamic semiconductor memory device superior in refresh characteristics 失效
标题翻译：动态半导体存储器件具有优异的刷新特性
公开(公告)号：US06452859B1
公开(公告)日：2002-09-17
申请号：US09795077
申请日：2001-03-01
申请人： Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
发明人： Hiroki Shimano , Katsumi Dosaka , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C29/783 , G11C8/08 , G11C8/10 , G11C8/14 , G11C11/4087 , G11C11/409 , G11C11/4097 , G11C29/806 , G11C29/846 , G11C2207/104 , G11C2207/2227
摘要： A sense operation by a sense amplifier circuit is carried out by selecting a pair of subword lines simultaneously and coupling each bit line in a pair to a memory cell. Since complementary data are stored into these two memory cells, the voltage between the bit lines in a pair in a sense operation can be set large enough to allow increase of the refresh interval. Therefore, power consumption in a data retaining mode can be reduced.
摘要翻译：通过同时选择一对子字线并将每对位线耦合到存储单元来执行读出放大器电路的感测操作。由于互补数据被存储到这两个存储单元中，所以在感测操作中成对的位线之间的电压可以被设置得足够大以允许刷新间隔的增加。因此，可以减少数据保持模式中的功耗。

36. 发明授权

US06429495B2 Semiconductor device with address programming circuit 失效
标题翻译：具有地址编程电路的半导体器件
公开(公告)号：US06429495B2
公开(公告)日：2002-08-06
申请号：US09208478
申请日：1998-12-10
申请人： Tsukasa Ooishi , Hiroki Shimano , Shigeki Tomishima
发明人： Tsukasa Ooishi , Hiroki Shimano , Shigeki Tomishima
IPC分类号： H01L2976
CPC分类号： G11C17/16 , G11C17/18 , H01L23/525 , H01L27/10897 , H01L29/66825 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.
摘要翻译：为了提供一种没有激光吹扫的地址编程装置，在半导体衬底上形成第一薄栅氧化膜，在其上形成第一栅电极，在其上形成第二厚栅极氧化膜，第二栅电极形成在其上。这种器件串联连接到相反极性的MOS晶体管，并且这种装置被交叉连接在一起以形成锁存电路。要编程的数据及其反转版本被写入编程装置。根据电源接通时锁存器的重量变化，读取编程信息。

37. 发明授权

US06404684B2 Test interface circuit and semiconductor integrated circuit device including the same 失效
标题翻译：测试接口电路和包括其的半导体集成电路器件
公开(公告)号：US06404684B2
公开(公告)日：2002-06-11
申请号：US09741147
申请日：2000-12-21
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G01R31/3172 , G01R31/31723 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/28 , G11C29/48 , G11C2029/0401
摘要： In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.
摘要翻译：在布置在嵌入式存储器和测试数据输入/输出（I / O））端子之间的测试接口电路中，布置用于连续存储测试数据的先进先出电路，用于控制从嵌入式存储器读取的数据的等待时间。用于嵌入式存储器的测试接口电路可以减少测试数据I / O端子的数量，并且可以增加可执行测试模式。

38. 发明授权

US06377483B1 Semiconductor memory device having improved memory cell and bit line pitch 失效
公开(公告)号：US06377483B1
公开(公告)日：2002-04-23
申请号：US09769416
申请日：2001-01-26
申请人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
发明人： Kazutami Arimoto , Hiroki Shimano , Toshinori Morihara
IPC分类号： G11C1124
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14 , H01L27/10897
摘要： Tow bit lines are arranged in each column in which memory cells are disposed. For selecting a first group sub-word line, only a sense amplifier on one sense amplifier band is activated and for selecting a second group sub-word line, only a sense amplifier on the other sense amplifier band is activated. A storage node is formed under a bit line.

39. 发明授权

US08971079B2 Inverter device 有权
标题翻译：变频器
公开(公告)号：US08971079B2
公开(公告)日：2015-03-03
申请号：US13638287
申请日：2011-03-31
申请人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
发明人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
IPC分类号： H02M3/24 , H02M7/5387
CPC分类号： H02M7/5387
摘要： An inverter device includes an inverter circuit, a control circuit, a first drive circuit, a second drive circuit, first and second photocouplers, and a signal switching part. The signal switching part directly transmits the first and second signals outputted from the first photocoupler and the second photocoupler to the corresponding first and second drive circuits respectively when at least one of the first and second signals is an OFF command.
摘要翻译：逆变器装置包括逆变器电路，控制电路，第一驱动电路，第二驱动电路，第一和第二光电耦合器以及信号切换部。当第一和第二信号中的至少一个是OFF命令时，信号切换部分分别将从第一光电耦合器和第二光电耦合器输出的第一和第二信号分别发送到对应的第一和第二驱动电路。

40. 发明授权

US08462251B2 Solid-state image sensor device and differential interface thereof 有权
标题翻译：固态图像传感器装置及其差分接口
公开(公告)号：US08462251B2
公开(公告)日：2013-06-11
申请号：US13542431
申请日：2012-07-05
申请人： Hiroki Shimano
发明人： Hiroki Shimano
IPC分类号： H04N5/335
CPC分类号： H04N5/3745 , H04N5/3577 , H04N5/3698 , H04N5/378
摘要： A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made.
摘要翻译：固态图像传感器装置包括用于输出正在拍摄的图像的模拟信号的图像传感器部分; 多个AD转换器部分，相对于图像传感器部分的列方向布置，用于将模拟信号转换成数字信号; 用于控制图像传感器部分和AD转换器部分的驱动电路部分; 以及多个差分接口部分，用于将由AD转换器部分转换的数字信号作为差分输出信号发送到外部设备。每个差分接口部分包括当进行操作模式切换时可操作的电流值转换电路和失调电压保持电路。

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