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31. 发明授权

US5747780A Apparatus for conveying and processing a wafer in a physically contact-free state 失效
标题翻译：用于在物理接触的状态下输送和处理晶片的装置
公开(公告)号：US5747780A
公开(公告)日：1998-05-05
申请号：US600639
申请日：1996-02-13
申请人： Yoshiyuki Shioyama , Masako Hori , Koji Kimura
发明人： Yoshiyuki Shioyama , Masako Hori , Koji Kimura
IPC分类号： B65G54/02 , B65G43/00 , B65G49/07 , H01L21/677 , H02K41/02 , H05B6/10
CPC分类号： H01L21/67784 , Y10S414/137 , Y10S414/138 , Y10S414/14
摘要： At the front side of a wafer cassette fitted to a wafer feeding unit of a magnetic levitation wafer conveying device, a wafer stopper for preventing the wafer waiting in the wafer cassette from popping out is provided. The wafer supplied from the magnetic levitation conveying device is supplied into the reaction chamber by magnetic force, and is directly held in the reaction chamber by this magnetic force. Since the wafer stopper is positioned between the wafer cassette fitted in the wafer feeding unit and the starting end of the wafer conveying route, the wafer waiting in the wafer cassette next to the wafer to be conveyed is prevented from popping out together with the wafer to be conveyed. Moreover, the wafer conveyed by the magnetic force can be directly held in the reaction chamber in heated state.
摘要翻译：在安装在磁悬浮晶片输送装置的晶片供给单元的晶片盒的前侧，设置有用于防止晶片盒中的晶片等待突出的晶片止动器。从磁悬浮输送装置供给的晶片通过磁力供给到反应室，并通过该磁力直接保持在反应室内。由于晶片止动器位于装配在晶片馈送单元中的晶片盒和晶片输送路径的起始端之间，因此可以防止在晶片盒中等待被输送晶片的晶片与晶片一起弹出被传达。此外，通过磁力传送的晶片可以在加热状态下直接保持在反应室中。

32. 发明授权

US5691593A Piezoelectric/electrostrictive actuator having at least one piezoelectric/electrostrictive film 失效
标题翻译：具有至少一个压电/电致伸缩膜的压电/电致伸缩致动器
公开(公告)号：US5691593A
公开(公告)日：1997-11-25
申请号：US392083
申请日：1995-02-22
申请人： Yukihisa Takeuchi , Koji Kimura , Masato Komazawa
发明人： Yukihisa Takeuchi , Koji Kimura , Masato Komazawa
IPC分类号： B41J2/14 , B41J2/16 , H01H57/00 , H01L41/09 , H01L41/314 , H01L41/335 , H01L41/39 , H01L41/08
CPC分类号： B41J2/161 , B41J2/14233 , B41J2/14274 , B41J2/1612 , B41J2/1623 , B41J2/1631 , B41J2/1632 , B41J2/1634 , B41J2/1642 , B41J2/1643 , B41J2/1645 , B41J2/1646 , H01L41/0973 , H01L41/314 , B41J2002/14258 , H01H2057/006 , H01H57/00 , H01L41/335 , Y10T29/42
摘要： A piezoelectric/electrostrictive actuator including a ceramic substrate, and at least one piezoelectric/electrostrictive actuator unit formed on at least a portion of at least one surface of the substrate, each piezoelectric/electrostrictive actuator unit having a first electrode film, a piezoelectric/electrostrictive film and a second electrode film which are laminated in the order of description, with the piezoelectric/electrostrictive actuator unit formed on the substrate by heat treatment.
摘要翻译：一种包括陶瓷基板的压电/电致伸缩致动器以及形成在基板的至少一个表面的至少一部分上的至少一个压电/电致伸缩致动器单元，每个压电/电致伸缩致动器单元具有第一电极膜，压电/电致伸缩膜和第二电极膜，按照说明书的顺序层压，通过热处理在基板上形成压电/电致伸缩致动器单元。

33. 发明授权

US5675173A Semiconductor device having a trench for isolating elements and a trench for applying a potential to a substrate 失效
标题翻译：具有用于隔离元件的沟槽和用于向衬底施加电位的沟槽的半导体器件
公开(公告)号：US5675173A
公开(公告)日：1997-10-07
申请号：US588322
申请日：1996-01-18
申请人： Hirofumi Kawai , Hiroyuki Miyakawa , Koji Kimura
发明人： Hirofumi Kawai , Hiroyuki Miyakawa , Koji Kimura
IPC分类号： H01L21/76 , H01L21/74 , H01L21/763 , H01L29/10 , H01L29/06
CPC分类号： H01L29/1087 , H01L21/743 , H01L21/763
摘要： The opening width of an element isolating trench is Wa'. The opening width of a substrate potential setting trench is Wb'. When the maximum film thickness of a polysilicon film lying on the side wall of each of the trenches is set to t, the opening width Wa' of the element isolating trench and the opening width Wb' of the substrate potential setting trench satisfies a condition that (Wa'-2t) 2t. A silicon oxide film covers the entire portion of the internal surface of the element isolating trench and covers the internal surface of the substrate potential setting trench except the bottom portion thereof. Therefore, the polysilicon film in the element isolating trench is set in the electrically floating state and the polysilicon film in the substrate potential setting trench is connected to the semiconductor substrate.
摘要翻译：元件隔离沟槽的开口宽度为Wa'。衬底电位设定沟槽的开口宽度为Wb'。当位于每个沟槽的侧壁上的多晶硅膜的最大膜厚设置为t时，元件隔离沟槽的开口宽度Wa'和衬底电位设定沟槽的开口宽度Wb'满足以下条件：（Wa'-2t）<（Wb'-2t）和Wa'> 2t。氧化硅膜覆盖元件隔离沟槽的内表面的整个部分，并且覆盖衬底电位设定沟槽的除了其底部之外的内表面。因此，元件隔离沟槽中的多晶硅膜被设置为电浮置状态，并且衬底电位设定沟槽中的多晶硅膜连接到半导体衬底。

34. 发明授权

US5665616A Process of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US5665616A
公开(公告)日：1997-09-09
申请号：US731012
申请日：1996-10-09
申请人： Koji Kimura , Hiroshi Naruse
发明人： Koji Kimura , Hiroshi Naruse
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L27/0623 , H01L21/8249
摘要： In the Bi-CMOS process of manufacturing a semiconductor device by an effective combination of a bipolar transistor manufacturing process and a CMOS transistor manufacturing process in the case of the formation of a silicide film on a Bi-CMOS device, in which the bipolar transistor having an inner base region made of a silicon film grown by epitaxy and the MOS transistor having silicide formed on the gate electrode, source region and drain region in a self-aligned manner therewith are formed on the same semiconductor substrate, while the silicon film of the inner base region is epitaxially grown in a step, a silicon film is also epitaxially grown on the source/drain regions at the same time in the same step.
摘要翻译：在双极晶体管制造工艺和CMOS晶体管制造工艺的有效组合的Bi-CMOS工艺中，在Bi-CMOS器件上形成硅化物膜的情况下，其中双极晶体管具有通过外延生长的硅膜制成的内基区域和在其自对准方式上形成在栅电极，源区和漏区上的具有硅化物的MOS晶体管形成在同一半导体衬底上，而硅膜内部基极区域在步骤中外延生长，在同一步骤中同时在源极/漏极区域上外延生长硅膜。

35. 发明授权

US5604371A Semiconductor device with an insulation film having an end covered by a conductive film 失效
标题翻译：具有绝缘膜的半导体器件，其端部被导电膜覆盖
公开(公告)号：US5604371A
公开(公告)日：1997-02-18
申请号：US421795
申请日：1995-04-14
申请人： Koji Kimura , Yuichi Nakashima , Hiroshi Kawamoto
发明人： Koji Kimura , Yuichi Nakashima , Hiroshi Kawamoto
IPC分类号： H01L21/768 , H01L21/8249 , H01L29/41
CPC分类号： H01L21/8249 , H01L21/76895
摘要： In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out. Thus, formation of residue on the side-wall of the second conductive film, on the stepped portions formed as covering the first conductive film, can be avoided. In a later step, the pattern of the second conductive film which covers the stepped portion is removed by etching.
摘要翻译：在半导体器件中，在半导体衬底的元件区域上形成由例如多晶硅制成的第一导电膜。绝缘膜形成在半导体衬底上，用于至少覆盖第一导电膜。第二导电膜至少覆盖绝缘膜的端部。第一导电膜用作MOS晶体管的栅电极，第二导电膜用作覆盖和保护绝缘膜的端部和双极晶体管的引出电极的保护膜。绝缘膜的端部由通过图案化例如由多晶硅制成的导电层获得的第二导电膜覆盖和保护。此外，导电层被图案化，使得形成在绝缘膜上的阶梯部分和绝缘膜的端部被覆盖，并且使用该图案进行各向异性蚀刻。因此，可以避免在形成为覆盖第一导电膜的阶梯部分上在第二导电膜的侧壁上形成残留物。在后续步骤中，通过蚀刻去除覆盖阶梯部分的第二导电膜的图案。

36. 发明授权

US5376857A Piezoelectric device 失效
标题翻译：压电元件
公开(公告)号：US5376857A
公开(公告)日：1994-12-27
申请号：US206939
申请日：1994-03-07
申请人： Yukihisa Takeuchi , Koji Kimura
发明人： Yukihisa Takeuchi , Koji Kimura
IPC分类号： B06B1/06 , B41J2/14 , H01L41/08 , H01L41/09 , H01L41/113
CPC分类号： H01L41/0973 , B41J2/14233 , B41J2002/14258 , B41J2002/14387
摘要： A piezoelectric device (1) includes an at least locally thin-walled ceramic substrate (2) and at least one piezoelectric transducer (3) on the substrate (2). The piezoelectric transducer (3) includes a lower electrode layer (4), a piezoelectric layer (5) and an upper electrode layer (6) which are sequentially laminated with each other. The piezoelectric layer (5) has a dimension which is sufficient to cover substantially completely the lower electrode layer (4). The piezoelectric layer (5) has at least one edge (7) which protrudes beyond the lower electrode layer (4) and which is at least locally incompletely bonded to the ceramic substrate (2).
摘要翻译：压电器件（1）包括至少局部薄壁陶瓷衬底（2）和在衬底（2）上的至少一个压电换能器（3）。压电换能器（3）包括相互层叠的下电极层（4），压电层（5）和上电极层（6）。压电层（5）的尺寸足以完全覆盖下电极层（4）。压电层（5）具有至少一个突出超过下电极层（4）的边缘（7），并且至少局部地不完全地结合到陶瓷衬底（2）上。

37. 发明授权

US5239347A Image forming apparatus having recording material carrying member and movable assisting member 失效
标题翻译：具有记录材料承载构件和活动辅助构件的图像形成装置
公开(公告)号：US5239347A
公开(公告)日：1993-08-24
申请号：US773267
申请日：1991-10-09
申请人： Shinichi Onodera , Kiyoharu Tanaka , Hajime Suzuki , Koji Kimura
发明人： Shinichi Onodera , Kiyoharu Tanaka , Hajime Suzuki , Koji Kimura
IPC分类号： G03G15/00 , G03G15/01 , G03G15/16 , G03G21/14
CPC分类号： G03G15/1655 , G03G15/0131 , G03G2215/0154 , G03G2215/018
摘要： An image forming apparatus includes an image bearing member; a recording material carrying member for carrying a recording material; an image transfer device for transferring an image from the image bearing member to the recording material carried on the recording material carrying member; an assisting member for assisting the recording material to be carried on the recording material carrying member, the assisting member being movable to and away from the recording material carrying member; wherein the assisting member is in contact with the recording material carrying member after completion of an image forming operation and before start of next image forming operation.
摘要翻译：图像形成装置包括：图像承载部件; 用于承载记录材料的记录材料承载构件; 图像转印装置，用于将图像从图像承载部件转印到承载在记录材料承载部件上的记录材料; 辅助构件，用于辅助记录材料携带在记录材料承载构件上，辅助构件可移动到远离记录材料承载构件; 其中所述辅助构件在完成图像形成操作之后并且在下一图像形成操作开始之前与所述记录材料承载构件接触。

38. 发明授权

US5126615A Piezoelectric/electrostrictive actuator having at least one piezoelectric/electrostrictive film 失效
标题翻译：具有至少一个压电/电绝缘膜的压电/电致动器
公开(公告)号：US5126615A
公开(公告)日：1992-06-30
申请号：US672330
申请日：1991-03-20
申请人： Yukihisa Takeuchi , Koji Kimura
发明人： Yukihisa Takeuchi , Koji Kimura
IPC分类号： H01L41/083 , H01L41/09 , H01L41/22 , H02N2/00
CPC分类号： H01L41/094 , H01L41/081 , H01L41/0933
摘要： A piezoelectric/electrostrictive actuator having at least one piezoelectric/electrostrictive unit each including a first electrode film, a piezoelectric/electrostrictive film and a second electrode film which are superposed on each other on a ceramic substrate, or at least one piezoelectric/electrostrictive unit each including a plurality of patterned spaced-apart electrode film strips formed on a ceramic substrate, and a plurality of patterned spaced-apart piezoelectric/electrostrictive film strips each formed on the ceramic substrate and disposed between and in contact with adjacent ones of the electrode film strips. The ceramic substrate includes ceramic particles and grain boundaries defined by the ceramic particles. Lead is included in the grain boundaries which exist in at least a selected portion of the ceramic substrate on which the unit or units is/are disposed.

39. 发明授权

US08945698B2 Honeycomb structure and method for manufacturing the same 有权
标题翻译：蜂窝结构及其制造方法
公开(公告)号：US08945698B2
公开(公告)日：2015-02-03
申请号：US12854379
申请日：2010-08-11
申请人： Koji Kimura , Takuya Nunome , Shuhei Fujita
发明人： Koji Kimura , Takuya Nunome , Shuhei Fujita
IPC分类号： B01D46/24 , B28B11/00 , B32B3/12 , C04B38/00
CPC分类号： B28B11/007 , B01D46/244 , B01D46/2459 , B32B3/12 , C04B35/195 , C04B38/0006 , C04B38/0012 , C04B2235/3217 , C04B2235/3218 , C04B2235/3418 , C04B2235/3445 , C04B2235/349 , Y10T156/1003 , Y10T428/24149 , C04B38/0054
摘要： A honeycomb structure includes porous partition walls via which a plurality of cells constituting through channels for a fluid are partitioned; and an outer peripheral wall positioned in the outermost periphery of the structure. Open frontal areas of predetermined cells in an end face of the structure on a fluid inlet side thereof and open frontal areas of remaining cells an end face of the structure on a fluid outlet side thereof are provided with plugged portions. Bubbles are formed in the plurality of plugged portions, and the center of each of the bubbles is positioned in a predetermined region of each of the plugged portions along the central axis direction thereof.
摘要翻译：蜂窝结构体包括多孔分隔壁，多个分隔壁通过通道形成的多个单元; 以及位于该结构的最外周的外周壁。在其流体入口侧的结构的端面中打开预定单元的正面区域，并且在其流体出口侧的结构的端面上设置有封闭部分，并且剩余单元的开放的正面区域。在多个堵塞部分中形成气泡，并且每个气泡的中心沿其中心轴线方向位于每个插塞部分的预定区域中。

40. 发明申请

US20130120034A1 Voltage Controlled Oscillator Calibration 有权
标题翻译：压控振荡器校准
公开(公告)号：US20130120034A1
公开(公告)日：2013-05-16
申请号：US13298057
申请日：2011-11-16
申请人： Koji Kimura , Alireza Zolfaghari
发明人： Koji Kimura , Alireza Zolfaghari
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A mobile communication device is provided that has a transceiver including a voltage controlled oscillator (VCO) and a calibration circuit for calibrating the VCO. The calibration circuit includes a logic block configured to estimate a calibration value for a tuning of the VCO to a desired frequency, and an asynchronous counter configured to execute a counting sequence to identify a frequency of the VCO after the tuning of the VCO using the calibration value, where the calibration circuit is configured to determine a tuned calibration value for producing the desired frequency from the counting sequence.
摘要翻译：提供一种具有收发器的移动通信设备，该收发器包括压控振荡器（VCO）和用于校准VCO的校准电路。校准电路包括被配置为估计用于将VCO调谐到期望频率的校准值的逻辑块，以及被配置为执行计数序列以在使用校准调谐VCO之后识别VCO的频率的异步计数器值，其中校准电路被配置为确定用于从计数序列产生期望频率的调谐校准值。

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