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31. 发明申请

US20090222225A1 IDDQ TEST APPARATUS AND TEST METHOD 失效
标题翻译： IDDQ测试装置和测试方法
公开(公告)号：US20090222225A1
公开(公告)日：2009-09-03
申请号：US12391210
申请日：2009-02-23
申请人： Shoji Kojima , Yasuo Furukawa
发明人： Shoji Kojima , Yasuo Furukawa
IPC分类号： G01R19/00 , G06F17/18
CPC分类号： G01R31/3008
摘要： Multiple non-defective samples of a DUT are selected. A quiescent power supply current (IDDQ) is measured for each of test vectors which are switched, for each of the non-defective samples. Statistical IDDQ values are measured in increments of the test vectors, and first array data is created including identifiers for the test vectors and the statistical IDDQs as elements. The first array data is sorted using the IDDQ value as a key so as to create second array data. The difference in quiescent power supply current is calculated by making difference between adjacent current elements of the second array data, so as to create third array data including the identifiers for the test vectors and the differences of current value as the elements.The third array data is sorted using the difference in current value as a key, and creates fourth array data.
摘要翻译：选择DUT的多个无缺陷样本。针对每个无缺陷样本切换的每个测试向量测量静态电源电流（IDDQ）。以测试向量的增量测量统计IDDQ值，并且创建包括测试向量和统计IDDQ作为元素的标识符的第一阵列数据。使用IDDQ值作为关键字对第一个数组数据进行排序，以创建第二个数组数据。通过使第二阵列数据的相邻电流元件之间的差异来计算静态电源电流的差异，从而创建包括测试矢量的标识符和当前值的差异作为元件的第三阵列数据。使用当前值的差作为关键字对第三个数组数据进行排序，并创建第四个数组数据。

32. 发明授权

US07576571B2 Potential comparator and test apparatus 失效
标题翻译：电位比较器和测试仪器
公开(公告)号：US07576571B2
公开(公告)日：2009-08-18
申请号：US11845752
申请日：2007-08-27
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K5/24
CPC分类号： G01R31/31924
摘要： The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object 2, a high-threshold side divided-voltage generating section 5 that acquires the differential signal from each of the input wires 3 and 4 and generates and outputs the first divided voltage and the second divided voltage that are a divided voltage based on a predetermined high threshold potential VOH and an electric potential of the acquired differential signal, a high-threshold side potential comparator 6 that derives a magnitude relation between the first and the second divided voltages output from the high-threshold side divided-voltage generating section 5. The high-threshold side divided-voltage generating section 5 includes a first divided-voltage generating section 16 and a second divided-voltage generating section 17, which respectively generate the first and the second divided voltages of a value in which a magnitude relation between the first and the second divided voltages in the high-threshold side potential comparator 6 corresponds to a magnitude relation between a potential difference between a plus signal and a minus signal and a high threshold potential.
摘要翻译：电位比较器包括输入从测试对象2输出的差分信号的输入线3和4，高阈值侧分压产生部分5，其从每个输入线3和4获取差分信号，并产生和输出基于预定的高阈值电位VOH和所获取的差分信号的电位的分压的第一分压和第二分压，高阈值侧电位比较器6，其导出第一和第二分压从高阈值侧分压生成部5输出的第二分压。高阈值侧分压生成部5具备：分压生成部16和第二分压生成部17，第一和第二分压，其中第一和第二之间的幅度关系被划分高阈值侧电位比较器6中的电压对应于正信号与负信号之间的电位差与高阈值电位之间的大小关系。

33. 发明申请

US20090147274A1 Document generation method, document generation system, and printing system 审中-公开
标题翻译：文件生成方法，文件生成系统和打印系统
公开(公告)号：US20090147274A1
公开(公告)日：2009-06-11
申请号：US11901879
申请日：2007-09-19
申请人： Shoji Kojima , Yuki Nishida
发明人： Shoji Kojima , Yuki Nishida
IPC分类号： G06K15/02
CPC分类号： B41J11/0065 , G06F3/1208 , G06F3/1246 , G06F3/1284 , G06F3/1285
摘要： [Object] To control a protrusion amount which indicates an amount of protrusion of an image protruding to a surrounding portion of a sheet for printing when marginless printing is performed in accordance with the XHTML-print specification.[Solving Means] The UI processor 11 accepts designation of a size of a sheet for printing and designation of an amount of protrusion from the sheet for printing when marginless printing is performed. The XHTML document generation unit 12 generates an XHTML document including a size of an image to be printed which is specified in accordance with a scale factor used when marginless printing is performed in accordance with the XHTML-print specification, a print starting position of the image to be printed which is specified in accordance with the scale factor and the specified amount of protrusion, and designation of marginless printing.
摘要翻译：根据XHTML打印规格，当进行无边距打印时，控制指示突出到用于打印的纸张的周围部分的图像的突出量的突出量。 [解决方案]在执行无边距打印时，UI处理器11接受用于打印的片材的尺寸的指定和用于打印的片材的突出量的指定。 XHTML文档生成单元12生成包括根据XHTML打印规格执行无边距打印时所使用的比例因子指定的要打印的图像的大小的XHTML文档，图像的打印开始位置要根据比例因子和指定的突出量指定打印，并指定无边距打印。

34. 发明申请

US20090122344A1 Image processing apparatus and control method thereof 审中-公开
标题翻译：图像处理装置及其控制方法
公开(公告)号：US20090122344A1
公开(公告)日：2009-05-14
申请号：US12291780
申请日：2008-11-13
申请人： Shunsuke Oi , Shoji Kojima
发明人： Shunsuke Oi , Shoji Kojima
IPC分类号： G06F3/12
CPC分类号： H04N1/00795 , H04N1/00801 , H04N1/00811 , H04N1/00822 , H04N1/387 , H04N2201/0091
摘要： An image processing apparatus, connected to a display apparatus so as to receive an image containing characters and to output the received image at a reduction rate which is set, includes a character size determination unit which determines a character size of an image which is received, a display control unit which displays a reduction rate-related setting screen for performing a reduction rate-related setting which is related to the reduction rate to the display apparatus on the basis of the determined character size so that a recommended reduction rate-related setting in which a character size of an output image is in a predetermined range and a non-recommended reduction rate-related setting which is other than the recommended reduction rate setting can be distinguishable from each other, and a reduction rate-related setting receiving unit which receives the reduction rate-related setting using the reduction rate-related setting screen.
摘要翻译：一种图像处理装置，连接到显示装置，以便接收包含字符的图像，并以设定的缩小率输出接收到的图像，包括：字符尺寸确定单元，确定接收到的图像的字符大小; 显示控制单元，其基于所确定的字符尺寸，将与缩小率相关的缩小率相关设置显示在与所显示装置相关的缩小率相关设置屏幕上，使得推荐的缩小率相关设置在输出图像的字符大小在预定范围内，并且与推荐的缩小率设置不同的非推荐的减少率相关设置可以彼此区分，并且减速率相关设置接收单元接收使用减速率相关设定画面的减速率相关设定。

35. 发明授权

US07317336B2 Impedance matching circuit, input-output circuit and semiconductor test apparatus 失效
标题翻译：阻抗匹配电路，输入输出电路和半导体测试装置
公开(公告)号：US07317336B2
公开(公告)日：2008-01-08
申请号：US11326182
申请日：2006-01-05
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K19/0175
CPC分类号： H04L25/0278
摘要： A characteristic test of a DUT having a low transmission line driving capability can be performed with a simple configuration and low cost. An impedance matching circuit is connected between a transmission line and a DUT in an input-output circuit of a semiconductor test apparatus. The impedance matching circuit includes: a resistance; an analog computing unit which multiplies a voltage from one end of the resistance by a predetermined number, subtracts a voltage from the other end of the resistance from the voltage multiplied by the predetermined number and outputs a resultant voltage; and a buffer which outputs a signal from the analog computing unit with low impedance. The impedance matching circuit produces an output signal from the DUT with low impedance, thereby sufficiently driving the transmission line.
摘要翻译：具有低传输线驱动能力的DUT的特性测试可以以简单的结构和低成本进行。阻抗匹配电路连接在半导体测试装置的输入 - 输出电路中的传输线和DUT之间。阻抗匹配电路包括：电阻; 将来自电阻的一端的电压乘以预定数量的模拟计算单元，从电压乘以预定数量的电阻的另一端减去电压，并输出合成电压; 以及缓冲器，其输出来自具有低阻抗的模拟计算单元的信号。阻抗匹配电路从DUT产生低阻抗的输出信号，从而充分驱动传输线。

36. 发明授权

US06294949B1 Voltage drive circuit, voltage drive apparatus and semiconductor-device testing apparatus 有权
标题翻译：电压驱动电路，电压驱动装置及半导体装置检测装置
公开(公告)号：US06294949B1
公开(公告)日：2001-09-25
申请号：US09588615
申请日：2000-06-06
申请人： Shoji Kojima , Takashi Sekino
发明人： Shoji Kojima , Takashi Sekino
IPC分类号： G05F110
CPC分类号： G01R31/31703 , G01R31/318558 , G01R31/31924 , G01R31/31932 , H03F3/72 , H03K5/2418
摘要： A circuit includes a first current path formed by a resistance R2, a transistor Q2, a transistor Q5 and a resistance R5. When an input signal A is low, a current i4 flows through the first circuit and the circuit outputs a shift voltage shifted from a constant voltage. When the input signal is high, the circuit directly outputs the constant voltage VH. The circuit further includes a second current path formed by a resistance R3 and a transistor Q3. By running a simulation current through the second current path, the shift voltage is monitored by a comparator OP1, and the current i4 is adjusted.
摘要翻译：电路包括由电阻R2，晶体管Q2，晶体管Q5和电阻R5形成的第一电流路径。当输入信号A为低电平时，电流i4流过第一电路，并且电路输出从恒定电压偏移的移位电压。当输入信号为高电平时，电路直接输出恒压VH。电路还包括由电阻R3和晶体管Q3形成的第二电流路径。通过运行通过第二电流路径的模拟电流，由比较器OP1监视移位电压，并调整电流i4。

37. 发明授权

US08773141B2 Test apparatus and circuit module 有权
标题翻译：测试仪器和电路模块
公开(公告)号：US08773141B2
公开(公告)日：2014-07-08
申请号：US13082386
申请日：2011-04-07
申请人： Tsuyoshi Ataka , Shoji Kojima
发明人： Tsuyoshi Ataka , Shoji Kojima
IPC分类号： G01R31/02
CPC分类号： G01R31/2874
摘要： Provided are a first test substrate and a second test substrate opposing each other, a first test circuit testing a device under test and being disposed on a face of the first test substrate that faces the second test substrate, a second test circuit testing the device under test and being disposed on a face of the second test substrate that faces the first test substrate, and a sealing section that is formed by sealing a space between the first test substrate and the second test substrate to enclose the first test circuit and the second test circuit in a common space that is filled with coolant.
摘要翻译：提供了第一测试基板和第二测试基板，第一测试电路测试被测器件并且设置在面向第二测试基板的第一测试基板的表面上，第二测试电路测试该器件的第二测试电路测试并设置在面对第一测试基板的第二测试基板的表面上，以及密封部分，其通过密封第一测试基板和第二测试基板之间的空间来封装第一测试电路和第二测试电路在充满冷却剂的公共空间中。

38. 发明授权

US08575961B2 Multi-valued driver circuit 失效
标题翻译：多值驱动电路
公开(公告)号：US08575961B2
公开(公告)日：2013-11-05
申请号：US13501451
申请日：2009-10-13
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K19/00 , H04L27/04
CPC分类号： H04L25/0272 , H04L25/4917
摘要： A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.
摘要翻译：多值驱动器电路根据选择信号选择性地向传输线输出多个电压中的一个。存储电路存储定义多个电压的各个电平的设置数据。根据选择信号，选择器电路从存储在存储电路中的多个设置数据中选择一个。戴维宁终端电路输出与由选择器电路所选择的数据的高M位对应的电压。 R-2R梯形电路输出对应于由选择器电路所选择的数据的低Nl位的电压。

39. 发明授权

US08220947B2 Differential driver circuit 失效
标题翻译：差分驱动电路
公开(公告)号：US08220947B2
公开(公告)日：2012-07-17
申请号：US13002975
申请日：2009-10-14
申请人： Yasuyuki Arai , Shoji Kojima
发明人： Yasuyuki Arai , Shoji Kojima
IPC分类号： H03K19/086
CPC分类号： H03G1/0088 , G01R31/31706 , H03F3/45183 , H03F3/72 , H03F2203/45358
摘要： A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off.
摘要翻译：第一电流源将尾电流It提供给多个差分对。预驱动器将门信号输出到相应差分对的晶体管的栅极。预驱动器被配置为在使能状态和禁止状态之间切换状态。在使能状态下，预驱动器输出与差分信号对应的门信号。在禁止状态下，预驱动器输出具有指示相应差分对的晶体管关断的电平的门信号。

40. 发明申请

US20120161840A1 SR FLIP-FLOP 失效
公开(公告)号：US20120161840A1
公开(公告)日：2012-06-28
申请号：US13335458
申请日：2011-12-22
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K3/037 , H03K12/00
CPC分类号： H03K3/0375
摘要： An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S′ is asserted and an intermediate reset signal R′ is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S′ is negated, and the intermediate reset signal R′ is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is asserted and the intermediate reset signal R′ is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is negated and the intermediate reset signal R′ is asserted.
摘要翻译：输入优先级确定电路被配置为使得：（i）当置位信号S被确定并且复位信号R被否定时，中断设置信号S'被断言并且中间复位信号R'被否定; （ii）当设定信号S被否定并且复位信号R被断言时，中间设置信号S'被否定，并且中断复位信号R'被断言; （iii）当控制信号P指示设定的优先模式时，并且当设定信号S和复位信号R均被断言时，中间设定信号S'被置位，中间复位信号R'被否定; 和（iv）当控制信号P指示复位优先模式时，并且当设置信号S和复位信号R均被断言时，中间设置信号S'被否定，并且中间复位信号R'被断言。

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