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31. 发明授权

US06515365B2 Semiconductor device having a ground plane and manufacturing method thereof 有权
公开(公告)号：US06515365B2
公开(公告)日：2003-02-04
申请号：US09957020
申请日：2001-09-21
申请人： Kazuyuki Higashi , Noriaki Matsunaga
发明人： Kazuyuki Higashi , Noriaki Matsunaga
IPC分类号： H01L2352
CPC分类号： H01L23/53252 , H01L21/76834 , H01L21/76849 , H01L23/5222 , H01L23/53223 , H01L23/53228 , H01L23/53242 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator to cover surfaces of the first and second lower layer wirings, first and second connection wirings which are provided on the first interlayer film and include first and second films contacting the first and second lower layer wirings respectively, and a plate electrode which is continuously provided on the second connection wiring and includes at least the first film.

32. 发明授权

US08592890B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08592890B2
公开(公告)日：2013-11-26
申请号：US13004229
申请日：2011-01-11
申请人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
发明人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.
摘要翻译：根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。层叠体包括与绝缘膜交替堆叠的电极膜。层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。触点从端部的上方连接到电极膜。半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。电荷存储层设置在电极膜和半导体部件之间。穿透构件在层叠方向上刺穿端部。穿透构件不包含与电荷存储层相同的材料。

33. 发明申请

US20120028460A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120028460A1
公开(公告)日：2012-02-02
申请号：US13270668
申请日：2011-10-11
申请人： Makoto WADA , Kazuyuki Higashi
发明人： Makoto WADA , Kazuyuki Higashi
IPC分类号： H01L21/768
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与所述第一导电构件的上表面的一部分接触的第二导电构件; 形成在所述第一绝缘膜上以与所述第一导电构件的所述上表面的一部分接触并且包括除了Si之外的所述第一绝缘膜中包含的元素中的至少一种元素的第二绝缘膜; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

34. 发明授权

US08058730B2 Semiconductor device having a multilayered interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08058730B2
公开(公告)日：2011-11-15
申请号：US12239236
申请日：2008-09-26
申请人： Makoto Wada , Kazuyuki Higashi
发明人： Makoto Wada , Kazuyuki Higashi
IPC分类号： H01L29/06
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与第一导电构件的上表面的一部分接触的第二导电构件，形成在第一绝缘膜上以与第一导电构件的上表面的一部分接触的第二绝缘膜，以及包括除Si之外的第一绝缘膜中包含的元素中的至少一种元素; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

35. 发明申请

US20110180866A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110180866A1
公开(公告)日：2011-07-28
申请号：US12875678
申请日：2010-09-03
申请人： Toru MATSUDA , Kazuyuki Higashi
发明人： Toru MATSUDA , Kazuyuki Higashi
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/66833 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, an insulating film, a non-doped semiconductor film, a semiconductor pillar, a charge storage film, a contact, and a spacer insulating film. The stacked body is provided on the substrate. The stacked body includes a plurality of doped semiconductor films stacked. The insulating film is provided between the doped semiconductor films in a first region. The non-doped semiconductor film is provided between the doped semiconductor films in a second region. The semiconductor pillar pierces the stacked body in a stacking direction of the stacked body in the first region. The charge storage film is provided between the doped semiconductor film and the semiconductor pillar. The contact pierces the stacked body in the stacking direction in the second region. The spacer insulating film is provided around the contact.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，层叠体，绝缘膜，非掺杂半导体膜，半导体柱，电荷存储膜，接触和间隔绝缘膜。层叠体设置在基板上。堆叠体包括堆叠的多个掺杂半导体膜。绝缘膜设置在第一区域中的掺杂半导体膜之间。在第二区域中，在掺杂半导体膜之间设置非掺杂半导体膜。半导体柱在第一区域中沿层叠体的堆叠方向穿透层叠体。电荷存储膜设置在掺杂半导体膜和半导体柱之间。接触件在第二区域中沿层叠方向刺穿堆叠体。间隔绝缘膜设置在触点周围。

36. 发明申请

US20090206491A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206491A1
公开(公告)日：2009-08-20
申请号：US12361979
申请日：2009-01-29
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

37. 发明授权

US07242238B2 Drive circuit for voltage driven type semiconductor element 有权
标题翻译：用于电压驱动型半导体元件的驱动电路
公开(公告)号：US07242238B2
公开(公告)日：2007-07-10
申请号：US11077208
申请日：2005-03-11
申请人： Kazuyuki Higashi
发明人： Kazuyuki Higashi
IPC分类号： H03K17/687
CPC分类号： H03K17/166 , H03K17/0828
摘要： A drive circuit for a voltage driven type semiconductor element, includes: an electrical charge discharge unit that discharges electrical charge from a gate terminal of a voltage driven type semiconductor element when the voltage driven type semiconductor element is turned OFF; and an electrical discharge control unit that detects a time variation of a collector voltage of the voltage driven type semiconductor element, and controls electric discharge by the electrical charge discharge unit according to the time variation of the collector voltage which has been detected.
摘要翻译：一种用于电压驱动型半导体元件的驱动电路，包括：电压放电单元，当电压驱动型半导体元件断开时，从电压驱动型半导体元件的栅极端子排出电荷; 以及放电控制单元，其检测所述电压驱动型半导体元件的集电极电压的时间变化，并且根据所检测的集电极电压的时间变化来控制所述电荷放电单元的放电。

38. 发明申请

US20070115038A1 Driver for voltage driven type switching element 有权
标题翻译：用于电压驱动型开关元件的驱动器
公开(公告)号：US20070115038A1
公开(公告)日：2007-05-24
申请号：US11601313
申请日：2006-11-17
申请人： Kazuyuki Higashi , Yoshinori Sato
发明人： Kazuyuki Higashi , Yoshinori Sato
IPC分类号： H03K3/00
CPC分类号： H03K17/0828 , H03K17/166 , H03K17/168 , H03K17/28 , H03K17/567
摘要： A driver apparatus for a voltage driven type switching element and a method for driving a voltage driven type switching element that discharge an electrical charge stored at the gate terminal of the voltage driven type switching element at a discharge rate. The discharge rate is controlled so that the change rate over time of the voltage between the collector terminal and the emitter terminal of the voltage driven type switching element approaches a predetermined change rate. Control of the change rate over time of the voltage between the collector terminal and the emitter terminal to attain the predetermined change rate is delayed for a predetermined delay time after start of the turn-off operation.
摘要翻译：一种用于电压驱动型开关元件的驱动器装置和用于驱动电压驱动型开关元件的方法，其以放电速率放电存储在电压驱动型开关元件的栅极端子处的电荷。控制放电率，使得电压驱动型开关元件的集电极端子和发射极端子之间的电压随时间的变化率接近预定的变化率。集电极端子和发射极端子之间的电压随时间的变化率达到预定变化率的控制在关断操作开始之后被延迟预定的延迟时间。

39. 发明申请

US20060154464A1 Semiconductor device and a method of fabricating a semiconductor device 审中-公开
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20060154464A1
公开(公告)日：2006-07-13
申请号：US11218722
申请日：2005-09-06
申请人： Kazuyuki Higashi
发明人： Kazuyuki Higashi
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76844 , H01L21/76801 , H01L21/76846 , H01L21/76867 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate; a porous low k dielectric disposed on the semiconductor substrate having a plurality of trenches therein, the porous low k dielectric having an effective dielectric constant of 3.0 or less; a plurality of barrier layers provided on each surface of the trenches, each of the barrier layers including a plurality of films having different film densities; a plurality of metal diffused regions provided in the porous low k dielectric and contacting the barrier layers; and a first conductor embedded in one of the trenches in contact with one of the barrier layer.
摘要翻译：半导体器件包括半导体衬底; 设置在其上具有多个沟槽的半导体衬底上的多孔低k电介质，所述多孔低k电介质具有3.0或更小的有效介电常数; 设置在沟槽的每个表面上的多个阻挡层，每个阻挡层包括具有不同膜密度的多个膜; 设置在所述多孔低k电介质中并接触所述阻挡层的多个金属扩散区域; 以及第一导体，其嵌入与所述阻挡层中的一个接触的所述沟槽中的一个。

40. 发明授权

US08916417B2 Method of manufacturing semiconductor device having chip stacks combined in relation to the number of chips having defects 有权
标题翻译：制造具有相对于具有缺陷的芯片数量组合的芯片堆叠的半导体器件的方法
公开(公告)号：US08916417B2
公开(公告)日：2014-12-23
申请号：US13601088
申请日：2012-08-31
申请人： Kazuyuki Higashi , Yoshiaki Sugizaki
发明人： Kazuyuki Higashi , Yoshiaki Sugizaki
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/4763 , H01L21/82 , H01L23/538 , H01L21/683 , H01L23/00 , H01L25/065 , H01L25/00 , H01L21/66 , H01L23/48
CPC分类号： H01L21/82 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L23/481 , H01L23/5384 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/73257 , H01L2224/83005 , H01L2224/9202 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2924/37001 , H01L2924/00 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.
摘要翻译：在堆叠形成多个半导体芯片的m个晶片之后，将m个晶片切割成半导体芯片，以形成堆叠有半导体芯片m的第一芯片堆叠，并且在堆叠n个晶片之后，将n个晶片切割形成半导体芯片堆叠的n个第二芯片堆叠。接下来，根据包括在第一芯片堆栈中的缺陷半导体芯片的数量对第一芯片堆叠进行分类，并且根据包括在第二芯片堆栈中的缺陷半导体芯片的数量对第二芯片堆栈进行分类。此外，将排序之后的第一芯片堆叠或第二芯片堆叠组合以形成第三芯片堆叠。

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