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31. 发明授权

US06301322B1 Balanced dual-edge triggered data bit shifting circuit and method 有权
标题翻译：平衡双边缘触发数据位移电路及方法
公开(公告)号：US06301322B1
公开(公告)日：2001-10-09
申请号：US09298799
申请日：1999-04-23
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/00
摘要： A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit. The inverters of each latching stage are alternatively enabled by coupling each one through a switching mechanism to a supply voltage terminal and a ground terminal, thereby shifting the data bit from one latch circuit to the other. The switching mechanism is rendered conductive based on the logic states of the two sets of edge-aligned complementary clock signals generated by the clock circuit.
摘要翻译：平衡双边沿触发位移电路包括产生低偏移或边沿对准的互补时钟信号的时钟电路，以及响应于互补时钟信号移位数据位的移位寄存器。时钟电路由两个时钟发生器形成，每个时钟发生器通过将两个缓冲电路的输入端子交替地耦合到电压供应端子和接地端子来产生边缘对准的互补时钟信号。传输门协调缓冲电路的输入端的耦合，使得由每个时钟发生器产生的结果输出时钟信号具有基本同时的时钟转换。移位寄存器由接收边沿对准的互补时钟信号的至少一个移位寄存器级形成。移位寄存器级包括两个锁存级，每个锁存级具有反相器，其输出耦合到锁存电路。每个锁存级的反相器可以通过将每一个通过开关机构耦合到电源电压端子和接地端子来实现，从而将数据位从一个锁存电路移位到另一个。基于由时钟电路产生的两组边缘对准的互补时钟信号的逻辑状态，使开关机构导通。

32. 发明授权

US06301164B1 Antifuse method to repair columns in a prefetched output memory architecture 有权
标题翻译：在预取输出存储器体系结构中修复列的Antifuse方法
公开(公告)号：US06301164B1
公开(公告)日：2001-10-09
申请号：US09648921
申请日：2000-08-25
申请人： Troy A. Manning , Chris G. Martin , Shubneesh Batra , Donald M. Morgan
发明人： Troy A. Manning , Chris G. Martin , Shubneesh Batra , Donald M. Morgan
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/812
摘要： A memory device having a first set of programmable elements programmed to store an address of a column having a bad memory cell, and a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a memory access. The SIT allows the memory device to selectively repair a bad memory cell within a column of memory cells accessed during a memory operation.
摘要翻译：一种存储器件，具有被编程为存储具有不良存储单元的列的地址的第一组可编程元件，以及被编程为存储坏存储器单元的时间间隔（SIT）的第二组可编程元件，指示在存储器访问中访问的多个存储器单元内的坏存储器单元的相对位置的错误存储器单元的SIT。 SIT允许存储器设备选择性地修复在存储器操作期间访问的存储器单元的列中的坏存储器单元。

33. 发明授权

US06230245B1 Method and apparatus for generating a variable sequence of memory device command signals 失效
标题翻译：用于产生可变序列的存储器件命令信号的方法和装置
公开(公告)号：US06230245B1
公开(公告)日：2001-05-08
申请号：US08798229
申请日：1997-02-11
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G06F1200
CPC分类号： G11C11/4076 , G11C7/22
摘要： A command generator for a dynamic random access memory decrements a counter from an initial counter value which is a function of the clock speed. The output of the counter is decoded to generate various command signals for the DRAM. In particular, each command signal is generated by a respective counter value, with the correspondency between counter values and command signals being a function of the clock speed. The counter decrements from larger initial values at higher clock speeds, and the command signals are generally issued by the decoder at higher counter values for higher clock speeds. As a result of the lack of correspondency between the timing of the command signals and the number of clock cycles occurring during a memory access, the timing of the command signals may be selected to optimize the speed of the DRAM desired despite substantial variations in clock speed.
摘要翻译：用于动态随机存取存储器的命令发生器从作为时钟速度的函数的初始计数器值递减计数器。计数器的输出被解码以产生用于DRAM的各种命令信号。特别地，每个命令信号由相应的计数器值产生，计数器值和命令信号之间的对应关系是时钟速度的函数。计数器在较高的时钟速度下从较大的初始值递减，并且命令信号通常由更高的计数器值由解码器以更高的时钟速度发出。由于命令信号的定时与在存储器访问期间发生的时钟周期的数目之间没有对应关系的结果，可以选择命令信号的定时以尽可能优化DRAM所需的速度，尽管时钟速度有很大变化。

34. 发明授权

US06202119B1 Method and system for processing pipelined memory commands 失效
标题翻译：处理流水线存储器命令的方法和系统
公开(公告)号：US06202119B1
公开(公告)日：2001-03-13
申请号：US08994461
申请日：1997-12-19
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G06F1200
CPC分类号： G11C7/1039
摘要： A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and a state machine to generate command signals from the latched command bits.
摘要翻译：一种用于在分组存储器件中处理流水线命令分组的方法和装置。命令分组最初存储在几个命令单元中的一个中，并且命令随后被耦合到公共命令处理器用于执行。命令单元各自包括用于存储命令分组的锁存器，计数器和启动命令生成器。计数器预先加载与在存储器件内的位置接收命令的定时对应的计数。计数器响应于使用命令包接收到的标志位开始计数。启动命令发生器接收计数器的计数，并且根据命令的类型（例如，“读取”或“写入”）解码不同的计数以及用于控制命令的操作的时钟信号的速度存储设备。当启动命令发生器解码计数时，它锁存所应用的命令包的命令位，并产生起始命令信号。因此，在标志信号之后产生对应于存储器命令的类型和时钟速度的延迟的起始命令信号。锁存的命令位和起始命令信号被施加到命令处理器，其使用定序器执行流水线中的命令以产生定时信号序列，以及状态机从锁存的命令位产生命令信号。

35. 发明授权

US06192578B1 Method for electrically coupling bond pads of a microelectronic device 有权
标题翻译：用于电耦合微电子器件的接合焊盘的方法
公开(公告)号：US06192578B1
公开(公告)日：2001-02-27
申请号：US09348557
申请日：1999-07-07
申请人： Troy A. Manning , Michael B. Ball
发明人： Troy A. Manning , Michael B. Ball
IPC分类号： H05K334
CPC分类号： H01L24/85 , H01L23/52 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/4556 , H01L2224/45599 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48477 , H01L2224/48599 , H01L2224/48699 , H01L2224/4911 , H01L2224/4917 , H01L2224/4942 , H01L2224/49426 , H01L2224/49429 , H01L2224/78301 , H01L2224/78313 , H01L2224/78318 , H01L2224/85051 , H01L2224/85181 , H01L2224/85203 , H01L2224/85207 , H01L2224/85951 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01047 , H01L2924/0106 , H01L2924/01079 , H01L2924/30105 , H01L2224/48227 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method and apparatus for electrically coupling bond pads on the surface of a microelectronic device. The apparatus can include a microelectronic device having at least two bond pads with a conductive member extending between the bond pads, external to the device. In one embodiment, the conductive member can be connected directly to the bond pads and can extend between the bond pads at or above the surface of the microelectronic device. In another embodiment, the conductive member can be connected on top of another conductive member previously attached to one of the bond pads. The conductive members can be attached to each other or to the bond pads with either ball bonds or wedge bonds to provide electrical signals to selected bond pads of the microelectronic device.
摘要翻译：一种用于电耦合微电子器件表面上的接合焊盘的方法和装置。该装置可以包括具有至少两个接合焊盘的微电子器件，该焊盘具有在器件外部的接合焊盘之间延伸的导电部件。在一个实施例中，导电构件可以直接连接到接合焊盘，并且可以在微电子器件的表面处或上方的接合焊盘之间延伸。在另一个实施例中，导电构件可以连接在预先连接到一个接合焊盘的另一个导电构件的顶部上。导电构件可以用球接合或楔形键彼此附接到接合焊盘，以向微电子器件的选定接合焊盘提供电信号。

36. 发明授权

US6105106A Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times 失效
标题翻译：计算机系统，存储器件和移位寄存器，包括具有串联连接的传输门的平衡开关电路，其被选择性地定时用于快速切换时间
公开(公告)号：US6105106A
公开(公告)日：2000-08-15
申请号：US2237
申请日：1997-12-31
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G11C7/10 , G11C19/00 , G11C19/38 , G06F13/00 , G11C11/407 , G11C11/413 , H03K17/04
CPC分类号： G11C19/38 , G11C19/00 , G11C7/1072
摘要： A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column. The balanced transfer gate circuit is operable to couple the first signal terminal to the second signal terminal in response to the clock signals. The transfer gates are selectively clocked or activated such that the switching speed is independent of the order in which the individual series connected past transistors or transfer gates are activated. A shift register circuit, a memory device, and a computer system utilizing such a balanced switching circuit are also described.
摘要翻译：平衡切换电路包括多个传输门，每个传输门具有输入端，输出端和适于接收控制信号的至少一个控制端。可以由诸如n沟道和p沟道金属氧化物半导体（MOS）晶体管的传输晶体管组成的每个传输门可以响应于控制信号将输入端耦合到输出端。多个传输门被布置成N行和N列，每行中的N个传输门的输入和输出端串联在第一信号端和第二信号端之间。每个传输门的控制端连接到适于接收相应时钟信号的N个时钟端之一。每个时钟端子耦合到每行仅一个传输门的控制端，每列中只有一个传输门。平衡传输门电路可操作以响应于时钟信号将第一信号端耦合到第二信号端。传输门被选择性地被定时或激活，使得开关速度独立于连接过去的晶体管或传输门的各个串联被激活的顺序。还描述了移位寄存器电路，存储器件和利用这种平衡开关电路的计算机系统。

37. 发明授权

US6094727A Method and apparatus for controlling the data rate of a clocking circuit 失效
公开(公告)号：US6094727A
公开(公告)日：2000-07-25
申请号：US103628
申请日：1998-06-23
申请人： Troy A. Manning
发明人： Troy A. Manning
IPC分类号： G11C11/407 , G06F1/08 , G06F1/12 , G06F12/00 , G06F13/42 , G11C7/10 , G11C7/22 , G06F1/06
CPC分类号： G11C7/109 , G06F1/08 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A data rate control circuit that is programmable between a first data rate and a second data rate. The data rate control circuit is formed by a clocking circuit and a switching circuit. The clocking circuit receives a first clock signal on a first input line and has a second input line which receives either the second clock signal or a steady state voltage. The switching circuit selectively couples the second clock signal or the steady state voltage to the clocking circuit. When the clocking circuit receives the second clock signal, the clocking circuit clocks at a double data rate, and when the clocking circuit receives the steady state voltage, the clocking circuit clocks at a single data rate. The switching circuit includes a switch that switches the output signal between the second clock signal and the steady state voltage. The clocking circuit can be any of many circuits known to those skilled in the art including a shift register or counter latch.

38. 发明授权

US6055193A Charge pump circuits and devices containing such 有权
标题翻译：电荷泵电路和包含此类的装置
公开(公告)号：US6055193A
公开(公告)日：2000-04-25
申请号：US348808
申请日：1999-07-07
申请人： Troy A. Manning , Manny K. F. Ma
发明人： Troy A. Manning , Manny K. F. Ma
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/146 , G11C11/4074
摘要： Circuits to convert an input voltage supply to an output voltage supply having a different magnitude or polarity. The circuits include a capacitor having a first terminal and a second terminal, a first switch coupled to the first terminal of the capacitor, and a second switch. The circuits further include a first node coupled between the second terminal of the capacitor and the second switch, and a third switch having a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch is adapted to couple the first terminal of the capacitor to the input supply voltage during a fill state and a second voltage level during a dump state. The second switch is adapted to couple the first node to a third voltage level during the fill state and present a high impedance to the first node during the dump state. The third switch is adapted to dump a charge from the first node to the second node during the dump state, thereby producing an output voltage at the second node.
摘要翻译：将输入电压源转换为具有不同大小或极性的输出电压源的电路。电路包括具有第一端子和第二端子的电容器，耦合到电容器的第一端子的第一开关和第二开关。电路还包括耦合在电容器的第二端子和第二开关之间的第一节点和具有耦合到第一节点的第一端子的第三开关和耦合到第二节点的第二端子。第一开关适于在充电状态期间将电容器的第一端子耦合到输入电源电压，并且在转储状态期间将第二电压电平耦合到第二电压电平。第二开关适于在填充状态期间将第一节点耦合到第三电压电平，并且在转储状态期间向第一节点呈现高阻抗。第三开关适于在转储状态期间将电荷从第一节点转储到第二节点，从而在第二节点产生输出电压。

39. 发明授权

US6005816A Sense amplifier for complementary or non-complementary data signals 有权
标题翻译：用于互补或非互补数据信号的感应放大器
公开(公告)号：US6005816A
公开(公告)日：1999-12-21
申请号：US196568
申请日：1998-11-19
申请人： Troy A. Manning , Chris G. Martin
发明人： Troy A. Manning , Chris G. Martin
IPC分类号： G11C7/06 , G01R19/00
CPC分类号： G11C7/065 , G11C7/062
摘要： A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifiers in the first stage so that the sense amplifiers compare a respective data signal to the reference voltage. The mode control circuit also alters the operation of the second stage. In the normal mode, the mode control circuit couples an output signal from the other sense amplifier in the first stage to a respective second input of each sense amplifier in the second stage so that the sense amplifiers receive at their differential inputs both of the complimentary output signals from each sense amplifier in the first stage. In the altered mode, the mode control circuit couples a data signal to the respective second input of each sense amplifier in the second stage so that the sense amplifiers compare an output signal from a respective sense amplifier in the first stage to a respective data signal.
摘要翻译：一种用于在正常模式或改变模式下放大数据信号的读出放大器。在正常模式下，数据信号必须彼此互补，而在改变的模式中，数据信号可以彼此互补，但不一定互补。读出放大器包括两个读出放大器级，其中第一个驱动第二个，每个读出放大器级包括两个相同的读出放大器电路。第一级中的每个读出放大器的第一输入接收相应的数据信号，并且第二级中的每个读出放大器的第一输入在第一级接收来自相应读出放大器的输出信号。在正常模式中，模式控制电路在第一级将每个其它数据信号耦合到每个读出放大器的相应第二输入端，使得读出放大器在它们的差分输入处接收两个互补数据信号。在改变的模式中，模式控制电路在第一级将参考电压耦合到读出放大器的第二输入端，使得读出放大器将相应的数据信号与参考电压进行比较。模式控制电路还改变第二级的操作。在正常模式中，模式控制电路在第二级将来自第一级的另一个读出放大器的输出信号耦合到第二级的每个读出放大器的相应的第二输入端，使得读出放大器在它们的差分输入处接收两个互补输出来自第一级的每个读出放大器的信号。在改变模式中，模式控制电路将数据信号耦合到第二级中每个读出放大器的相应第二输入端，使得读出放大器将来自第一级的相应读出放大器的输出信号与相应的数据信号进行比较。

40. 发明授权

US5969379A Memory and other integrated circuitry having a conductive interconnect line pitch of less than 0.6 micron 失效
标题翻译：存储器和具有小于0.6微米的导电互连线间距的其它集成电路
公开(公告)号：US5969379A
公开(公告)日：1999-10-19
申请号：US76328
申请日：1998-05-11
申请人： J. Wayne Thompson , Troy A. Manning
发明人： J. Wayne Thompson , Troy A. Manning
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/10 , H01L29/76 , H01L31/062 , H01L31/113
CPC分类号： H01L27/108
摘要： Integrated circuitry includes, a) a first array of electronic devices comprising a series of conductive runners extending outwardly of the memory array with adjacent runners having a device pitch of 0.6 micron or less in a pitch direction, b) a second array of electronic devices peripheral to the first array, the 0.6 pitch conductive runners of the first array extending into the second array, at least some of the conductive runners of the series having respective disjointed gaps therewithin within the second array, the gaps being aligned with one another in the second array, c) a cross running conductor extending substantially parallel with the pitch direction and over the aligned gaps within the second array, d) an insulating dielectric layer provided relative to the disjointed gaps within the second array; and e) a series of electrically conductive plugs provided within the insulating dielectric layer and running substantially perpendicular to the pitch direction within the second array, the conductive plugs respectively extending across the respective gaps between and electrically interconnecting the respective disjointed conductive runners within the second array, the cross running conductor extending elevationally over the conductive plugs. Memory integrated circuitry is also disclosed which incorporates electrically conductive plugs which electrically interconnect disjointed active area regions of different transistors in pitch cells.
摘要翻译：集成电路包括：a）电子器件的第一阵列，包括从存储器阵列向外延伸的一系列导电流道，相邻的流道在俯仰方向上具有0.6微米或更小的器件间距，b）第二阵列的电子器件外围所述第一阵列中的所述第一阵列的0.6节距导电流道延伸到所述第二阵列中，所述系列的至少一些所述导电流道在所述第二阵列内具有彼此不相交的间隙，所述间隙在所述第二阵列中在所述第二阵列中彼此对准阵列，c）交叉运行导体，其基本上平行于所述俯仰方向延伸并且在所述第二阵列内的所述对准的间隙上延伸; d）相对于所述第二阵列内的所述不相交的间隙提供的绝缘介电层; 以及e）一系列导电插塞，其设置在所述绝缘介电层内并且基本上垂直于所述第二阵列内的所述俯仰方向运行，所述导电插塞分别延伸穿过所述相应的间隙并将所述第二阵列内的相应不相交的导电流道电互连，交叉运行导体在导电插头上垂直延伸。还公开了一种存储器集成电路，其包括导电插头，其将间距单元中的不同晶体管的不相交的有源区域区域电互连。

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