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31. 发明授权

US06326260B1 Gate prespacers for high density, high performance DRAMs 失效
标题翻译：用于高密度，高性能DRAM的Gate Prepacers
公开(公告)号：US06326260B1
公开(公告)日：2001-12-04
申请号：US09599703
申请日：2000-06-22
申请人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
发明人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823462 , H01L27/10873
摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
摘要翻译：提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及所述多晶硅层在所述导体材料层上形成氮化物覆盖层形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

32. 发明授权

US06284666B1 Method of reducing RIE lag for deep trench silicon etching 失效
标题翻译：减少深沟槽硅蚀刻RIE滞后的方法
公开(公告)号：US06284666B1
公开(公告)日：2001-09-04
申请号：US09583963
申请日：2000-05-31
申请人： Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
发明人： Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/3065
摘要： A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,
摘要翻译：最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， <30：1）。该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。或者，通过非RIE蚀刻工艺去除钝化膜。可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。膜的受控厚度允许实现高纵横比结构的预定DT深度。

33. 发明授权

US07709882B2 Storage device with charge trapping structure and methods 失效
标题翻译：具有电荷捕获结构和方法的存储装置
公开(公告)号：US07709882B2
公开(公告)日：2010-05-04
申请号：US11255458
申请日：2005-10-20
申请人： Hang Liao , Zhizhang Chen , Alexander Govyadinov , Leslie Louis Szepesi, Jr. , Heon Lee
发明人： Hang Liao , Zhizhang Chen , Alexander Govyadinov , Leslie Louis Szepesi, Jr. , Heon Lee
IPC分类号： H01L29/788
CPC分类号： B82Y10/00 , G11B9/08 , G11B9/14 , G11B9/1409 , G11B9/1418 , G11B9/1436 , G11B11/08
摘要： A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.
摘要翻译：存储装置包括具有p-掺杂剂的第一半导体层和具有n-掺杂剂的第二半导体层，其设置在第一半导体层上，形成第一和第二半导体层之间的结。存储装置还包括设置在第二半导体层上的电荷捕获结构和导电栅极，其中导电栅极和电荷捕获结构相对于另一个迁移，其中施加在第二半导体层和导电栅极阱上的电场电荷捕获结构中的电荷。

34. 发明申请

US20050181293A1 Imprinting device and substrate holding device thereof 审中-公开
标题翻译：压印装置及其基板保持装置
公开(公告)号：US20050181293A1
公开(公告)日：2005-08-18
申请号：US10834371
申请日：2004-04-28
申请人： Heon Lee
发明人： Heon Lee
IPC分类号： H01L21/027 , G03C5/00 , G03F7/00 , G03G13/06 , G03G13/20
CPC分类号： B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： The present invention relates to an imprinting device for imprinting a pattern, and more particularly, to an imprinting device for imprinting a pattern to a size of nanometer or micrometer dimension. The imprinting device of the present invention is comprised of: a part for forming a hollow portion for accommodating a stamp formed with a pattern and transparent with respect to ultraviolet rays or infrared rays, and a base substrate formed with a polymer hardened by the ultraviolet rays or the infrared rays; an elastic plate made of an elastic material and forming a part of an inner wall of the hollow portion, the elastic plate which is so deformed by a pressure difference between inside and outside of the hollow portion that the stamp is pressed onto the polymer onto the base substrate in order that the pattern formed on a surface of the stamp is transcribed on the polymer; a transparent plate made of a material transparent with respect to the ultraviolet rays or the infrared rays and forming a part of another inner wall facing the elastic plate at the hollow portion, the transparent plate which transmits the ultraviolet rays or the infrared rays to the polymer formed with the pattern so that the polymer is hardened; and a part for discharging air in the hollow portion to be a low pressure state.
摘要翻译：本发明涉及一种用于压印图案的压印装置，更具体地说，涉及一种用于将图案压印成尺寸为纳米或微米尺寸的压印装置。本发明的压印装置包括：用于形成中空部分的部分，用于容纳形成有图案并且相对于紫外线或红外线透明的印模，以及形成有由紫外线硬化的聚合物的基底或红外线; 由弹性材料制成并形成中空部分的内壁的一部分的弹性板，弹性板通过中空部分的内部和外部之间的压力差而变形，使得压印在聚合物上的弹性板以使形成在印模表面上的图案转录在聚合物上; 由相对于紫外线或红外线透明的材料制成的透明板，并且在中空部分形成面对弹性板的另一内壁的一部分，透射板将紫外线或红外线透射到聚合物形成图案，使得聚合物硬化; 以及将中空部中的空气排出到低压状态的部分。

35. 发明授权

US06927092B2 Method of forming a shared global word line MRAM structure 有权
标题翻译：形成共享全局字线MRAM结构的方法
公开(公告)号：US06927092B2
公开(公告)日：2005-08-09
申请号：US10656758
申请日：2003-09-05
申请人： Heon Lee , Fred Perner
发明人： Heon Lee , Fred Perner
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L21/00
CPC分类号： G11C11/16 , G11C11/15
摘要： A method of forming a shared global word line MRAM structure is disclosed. The method includes, etching a trench in an oxide layer formed over a substrate, depositing an first liner material, anisotropically etching the deposited first liner material leaving the first liner material on edges of the trench and physically contacting a bottom of the trench, depositing an magnetic metal liner material, anisotropically etching the deposited magnetic metal liner material leaving the magnetic metal liner material over the first liner material on edges of the trench, so that the magnetic metal liner extends to and physically contacts the bottom of the trench, depositing a conductive layer;, and chemically, mechanically polishing the conductive layer.
摘要翻译：公开了一种形成共享全局字线MRAM结构的方法。该方法包括：蚀刻在衬底上形成的氧化物层中的沟槽，沉积第一衬里材料，各向异性地蚀刻沉积的第一衬垫材料，使第一衬垫材料留在沟槽的边缘上并物理接触沟槽的底部，磁性金属衬垫材料，各向异性地蚀刻离开磁性金属衬垫材料的沉积的磁性金属衬垫材料在沟槽边缘上的第一衬里材料上，使得磁性金属衬垫延伸到并物理接触沟槽的底部，沉积导电层;并且化学地，机械地抛光导电层。

36. 发明申请

US20050161431A1 Silicon carbide imprint stamp 失效
标题翻译：碳化硅印记邮票
公开(公告)号：US20050161431A1
公开(公告)日：2005-07-28
申请号：US10766646
申请日：2004-01-27
申请人： Heon Lee
发明人： Heon Lee
IPC分类号： C03C25/68
CPC分类号： C04B35/565 , B81C99/009 , B82Y10/00 , B82Y40/00 , C04B2235/602 , C04B2235/94 , G03F7/0002
摘要： A method of fabricating a silicon carbide imprint stamp is disclosed. A mold layer has a cavity formed therein. A spacer is formed in the cavity to reduce a first feature size of the cavity. A casting process is used to form a feature and a foundation layer connected with the feature. The spacer operatively reduces the first feature size of the feature to a second feature size that is less than the lithography limit. The foundation layer and the feature are unitary whole made from a material comprising silicon carbide (SiC), a material that is harder than silicon (Si) alone. Consequently, the silicon carbide imprint stamp has a longer service lifetime because it can endure several imprinting cycles without wearing out or breaking. The longer service lifetime makes the silicon carbide imprint stamp economically feasible to manufacture as the manufacturing cost can be recouped over the service lifetime.
摘要翻译：公开了一种制造碳化硅印记印模的方法。模具层中形成有空腔。间隔件形成在空腔中以减小空腔的第一特征尺寸。使用铸造工艺来形成与特征相连的特征和基础层。间隔件可以将特征的第一特征尺寸减小到小于光刻极限的第二特征尺寸。基础层和特征是由包括碳化硅（SiC）的材料制成的整体，其是单独比硅（Si）更硬的材料。因此，碳化硅印记印模具有更长的使用寿命，因为它可以承受几个压印周期而不会磨损或断裂。更长的使用寿命使得碳化硅印记印模经济上可行，因为制造成本可以在使用寿命内回收。

37. 发明申请

US20050111341A1 Molecular optoelectronic memory device 有权
标题翻译：分子光电存储器件
公开(公告)号：US20050111341A1
公开(公告)日：2005-05-26
申请号：US10721574
申请日：2003-11-25
申请人： Sean Zhang , Heon Lee
发明人： Sean Zhang , Heon Lee
IPC分类号： G11B9/14 , G11B7/00 , G11B7/0033 , G11B7/0045 , G11B7/24 , G11B11/00 , G11B11/08 , G11C11/35 , G11C11/42
CPC分类号： G11B11/00 , G11B7/0033 , G11B7/00455 , G11B7/24
摘要： Method for employing optical state-change organic polymer films as information-storage layers in optoelectronic, high-density memories, and high-density optoelectronic memories produced by the method. In certain embodiments, the optical state-change organic polymer films can be manufactured to exhibit two different, stable optical states, one transparent, and one light-absorbing and/or light-reflecting, that can be locally, stably, and reversibly induced by application of an electrical field. In various embodiments, information is digitally encoded in an information-storage layer as bits, the value of each bit represented by the optical state of an area of the information-storage layer corresponding to the bit. In various embodiments, the optical state of a small region of the information-storage layer can be determined by exposing the small region to visible light, and determining whether or not a photodiode layer in an information-storage medium below the information-storage layer generates an electrical current in response to illumination.
摘要翻译：在光电子，高密度存储器中使用光学状态变换有机聚合物膜作为信息存储层的方法，以及通过该方法制造的高密度光电存储器。在某些实施方案中，可以制造光学状态变化的有机聚合物膜以呈现两种不同的，稳定的光学状态，一种透明的，一种光吸收和/或光反射，其可以局部，稳定和可逆地由应用电场。在各种实施例中，信息在信息存储层中被数字地编码为比特，每个比特的值由对应于该比特的信息存储层的区域的光学状态表示。在各种实施例中，信息存储层的小区域的光学状态可以通过将小区域暴露于可见光来确定，并且确定在信息存储层下方的信息存储介质中的光电二极管层是否产生响应照明的电流。

38. 发明申请

US20050090056A1 A METHOD OF MAKING A MAGNETIC TUNNEL JUNCTION DEVICE 有权
标题翻译：一种制造磁性隧道连接装置的方法
公开(公告)号：US20050090056A1
公开(公告)日：2005-04-28
申请号：US10692612
申请日：2003-10-24
申请人： Heon Lee
发明人： Heon Lee
IPC分类号： H01L21/336 , H01L27/22 , H01L31/113 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.
摘要翻译：公开了制造磁性隧道结装置的方法。磁性隧道结装置包括磁性隧道结叠层和与磁性隧道结叠层的一部分接触的非导电间隔物。间隔件将磁性隧道结堆叠的一部分与用于与磁性隧道结叠层和顶部导体接触的通路的导电材料电绝缘。隔离器还可以防止底部导体和顶部导体之间的电短路。当磁性隧道结堆叠和自对准通孔彼此不对齐时，间隔件可以防止电气短路。

39. 发明申请

US20050018884A1 Fingerprint sensor, fabrication method thereof and fingerprint sensing system 审中-公开
标题翻译：指纹传感器及其制造方法及指纹感应系统
公开(公告)号：US20050018884A1
公开(公告)日：2005-01-27
申请号：US10898487
申请日：2004-07-22
申请人： Heon Lee , Don Lee
发明人： Heon Lee , Don Lee
IPC分类号： G01B7/28 , A61B5/117 , G06K9/00 , G06T1/00
CPC分类号： G06K9/00053
摘要： A fingerprint sensor of the present invention includes a substrate; a plurality of electrode patterns formed on the substrate for detecting an impedance signal in response to the contact of a fingerprint; and an insulating layer formed on the substrate including the electrode patterns.
摘要翻译：本发明的指纹传感器包括：基板; 形成在所述基板上的多个电极图案，用于响应于指纹的接触来检测阻抗信号; 以及形成在包括电极图案的基板上的绝缘层。

40. 发明申请

US20050018526A1 Phase-change memory device and manufacturing method thereof 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20050018526A1
公开(公告)日：2005-01-27
申请号：US10772141
申请日：2004-02-03
申请人： Heon Lee
发明人： Heon Lee
IPC分类号： H01L27/24 , H01L45/00 , G11C8/02
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/16
摘要： The present invention is to provide a phase change memory device having a new structure which can be easily manufactured by mass-production with a high yield rate, therefore, reducing the cost of process and providing reliable device characteristics, and a manufacturing method thereof. The present invention provides a phase-change memory device comprising: a lower dielectric layer; a lower electrode, at least a part of the lateral surface of the lower electrode being surrounded by the lower dielectric layer; a thin dielectric layer including a pore having smaller area than the top surface of the lower electrode, aligned to the top surface of the lower electrode and extending to the top surface of the lower electrode; and a phase-change resistor filling the pore and formed on the thin dielectric layer. In the proposed structure of the present invention, the pores or local damaged spots can provide a micro path of current and localize the phase-changing volume in the phase-change resistor. Thus, the phase-change memory device can be operated with very low power.
摘要翻译：本发明提供一种具有新结构的相变存储器件及其制造方法，该相变存储器件可以容易地通过批量生产以高产率制造，从而降低工艺成本并提供可靠的器件特性。本发明提供了一种相变存储器件，包括：下介电层; 下电极，下电极的侧表面的至少一部分被下电介质层包围; 包括具有比下电极的顶表面小的面积的孔的薄介电层，与下电极的顶表面对准并延伸到下电极的顶表面; 以及填充所述孔并形成在所述薄介电层上的相变电阻器。在本发明的所提出的结构中，孔或局部损坏的斑点可以提供微通路并使相变电阻器中的相变体积定位。因此，可以以非常低的功率来操作相变存储器件。

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