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31. 发明授权

US07205639B2 Semiconductor devices with rotated substrates and methods of manufacture thereof 有权
标题翻译：具有旋转基板的半导体器件及其制造方法
公开(公告)号：US07205639B2
公开(公告)日：2007-04-17
申请号：US11076080
申请日：2005-03-09
申请人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
发明人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
IPC分类号： H01L29/04 , H01L31/00
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/78
摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
摘要翻译：集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向在0至45度之间旋转的角度定向在基板上。诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

32. 发明申请

US20060163569A1 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US20060163569A1
公开(公告)日：2006-07-27
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

33. 发明申请

US20060113534A1 Test structure of semiconductor device 有权
公开(公告)号：US20060113534A1
公开(公告)日：2006-06-01
申请号：US11243595
申请日：2005-10-05
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

34. 发明申请

US20120074499A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20120074499A1
公开(公告)日：2012-03-29
申请号：US13296578
申请日：2011-11-15
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/08 , G03F1/38 , G03F1/48 , G06F17/50 , G03F1/00
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

35. 发明申请

US20100276759A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20100276759A1
公开(公告)日：2010-11-04
申请号：US12839750
申请日：2010-07-20
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/088 , H01L27/02 , G06F17/50 , H01L21/64
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

36. 发明授权

US07501651B2 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US07501651B2
公开(公告)日：2009-03-10
申请号：US11243595
申请日：2005-10-05
申请人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Roman Knoefler , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.
摘要翻译：提供了具有改善的测试可靠性的半导体器件的测试结构。测试结构包括彼此电隔离并且分别在其上形成有硅化的第一和第二结区的第一和第二有源区，形成在第一和第二结区的下部的半导体衬底或阱，以及具有不同于第一和第二接合区域的导电类型，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到第一和第二接合区域并被检测，并且形成在与金属的下部相同的高度上层或与半导体衬底相同的水平。

37. 发明申请

US20080142849A1 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US20080142849A1
公开(公告)日：2008-06-19
申请号：US11638067
申请日：2006-12-13
申请人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
发明人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
IPC分类号： H01L29/76
CPC分类号： H01L21/26513 , H01L27/027 , H01L29/0619 , H01L29/665 , H01L29/7833
摘要： An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.
摘要翻译： ESD保护器件包括半导体本体，形成在半导体本体中的沟道上的栅极，该沟道掺杂有第一导电类型的掺杂剂的第一浓度。第一源极/漏极区域形成在与栅极的第一边缘相邻的半导体本体的表面上，其中第一源极/漏极区域掺杂有与第一导电类型相反的第二导电类型的掺杂物，并且至少第一源/漏区的一部分掺杂有第一导电类型的掺杂剂。第二导电型掺杂物的浓度超过第一导电型掺杂剂的浓度，并且第一源极/漏极中的第一导电类型掺杂剂的浓度超过第一浓度。第二源极/漏极区域还形成在与栅极的第二边缘相邻的半导体本体的上表面处，其中第二源极/漏极区域掺杂有第二导电类型的掺杂物。

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