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31. 发明授权

US07035332B2 DCT/IDCT with minimum multiplication 失效
标题翻译： DCT / IDCT，最小乘法
公开(公告)号：US07035332B2
公开(公告)日：2006-04-25
申请号：US09924140
申请日：2001-08-07
申请人： Ouyang He , Li Sha , Shuhua Xiang , Ping Zhu , Yaojun Luo
发明人： Ouyang He , Li Sha , Shuhua Xiang , Ping Zhu , Yaojun Luo
IPC分类号： H04B1/66
CPC分类号： G06F17/147 , H04N19/423 , H04N19/43 , H04N19/61
摘要： A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.
摘要翻译：描述了用于图像信号的离散余弦变换和逆离散余弦变换（DCT / IDCT）的方法，装置，计算机介质和其他实施例。 DCT / IDCT模块包括多个不同的核。核心的一个实施例包括两组查找表，用于为DCT和IDCT功能提供乘法和加法运算。核心的另一实施例包括一组查找表，而核心的另一实施例不包括查找表。 DCT / IDCT模块提供前向DCT和IDCT功能，而不需要使用额外的乘法器。

32. 发明申请

US20050248590A1 Method and system for scaling, filtering, scan conversion, panoramic scaling, YC adjustment, and color conversion in a display controller 失效
标题翻译：在显示控制器中进行缩放，滤波，扫描转换，全景缩放，YC调整和颜色转换的方法和系统
公开(公告)号：US20050248590A1
公开(公告)日：2005-11-10
申请号：US11120443
申请日：2005-05-02
申请人： Yu Tian , Qifan Huang , Li Sha
发明人： Yu Tian , Qifan Huang , Li Sha
IPC分类号： G06F17/10 , G06T3/40 , G09G5/00 , G09G5/391 , H04N5/44 , H04N9/64 , H04N11/20
CPC分类号： H04N11/20 , G06T3/4007 , G06T3/4038 , G09G5/391 , G09G2340/0407 , H04N7/01 , H04N7/0122 , H04N7/0125 , H04N9/64 , H04N9/641 , H04N9/67 , H04N9/68
摘要： Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.
摘要翻译：公开了用于执行全景缩放的技术，其减少全景图像中的可见失真。此外，公开了用于执行组合YC调整和颜色转换的技术，通过减少当将YC调整和颜色转换实现为单独操作时所需的逻辑门数和存储缓冲器的数量来减小视频操纵硬件的尺寸和功率要求。

33. 发明授权

US08711019B1 Context-based adaptive binary arithmetic coding engine 有权
标题翻译：基于上下文的自适应二进制算术编码引擎
公开(公告)号：US08711019B1
公开(公告)日：2014-04-29
申请号：US13185354
申请日：2011-07-18
申请人： Guan-Ming Su , Leung Chung Lai , Wenchi Hsu , Qian Tang , Li Sha , Ching-Han Tsai
发明人： Guan-Ming Su , Leung Chung Lai , Wenchi Hsu , Qian Tang , Li Sha , Ching-Han Tsai
IPC分类号： H03M7/00
CPC分类号： H03M7/4006 , H04N19/13 , H04N19/61
摘要： A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.
摘要翻译：一种包括二值化模块，预测模块和移位模块的系统。编码模块被配置为使用上下文自适应二进制算术编码对符号进行编码，其中通过二元化语法元素来生成符号。预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。移位模块被配置为通过移位二进制化的语法元素R times来生成重新归一化的间隔范围，其中R是二进制化语法元素中的1之前的前导零的数量。编码模块被配置为基于重新归一化的间隔范围对符号之后的下一个符号进行编码。

34. 发明授权

US08587609B1 Accuracy-adaptive and scalable vector graphics rendering 有权
标题翻译：精度自适应和可缩放的矢量图形渲染
公开(公告)号：US08587609B1
公开(公告)日：2013-11-19
申请号：US12510834
申请日：2009-07-28
申请人： Haohong Wang , Yunsen Chin , Li Sha , Shuhua Xiang
发明人： Haohong Wang , Yunsen Chin , Li Sha , Shuhua Xiang
IPC分类号： G09G5/00 , G09G5/24 , G06T11/00
CPC分类号： G06T11/40 , G06T11/203 , G09G5/246 , G09G5/28
摘要： Embodiments of the present invention provide methods and associated architecture of accuracy adaptive and scalable vector graphics rendering including rendering a graphic comprising a plurality of line segments by processing each of the plurality of line segments in a first pass, and processing each of a plurality of pixels through which the plurality of line segments pass in a second pass, automatically detecting one or more rendering errors of the graphic, and correcting the one or more rendering errors. Other embodiments may be described and/or claimed.
摘要翻译：本发明的实施例提供了精度自适应和可缩放的矢量图形渲染的方法和相关架构，包括通过在第一遍中处理多个线段中的每一个来渲染包括多个线段的图形，以及处理多个像素多个线段通过其通过第二遍，自动检测图形的一个或多个渲染错误，以及校正一个或多个渲染错误。可以描述和/或要求保护其他实施例。

35. 发明授权

US08539120B1 System and method of video decoding using hybrid buffer 失效
标题翻译：使用混合缓冲区的视频解码系统和方法
公开(公告)号：US08539120B1
公开(公告)日：2013-09-17
申请号：US13662748
申请日：2012-10-29
申请人： Li Sha
发明人： Li Sha , Ching-Han Tsai , Chengjun Wang
IPC分类号： G06F3/00 , G06F13/00 , G06K9/36
CPC分类号： H04N19/433 , G06F5/065 , H04N19/426 , H04N19/44
摘要： In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.
摘要翻译：在一个实施例中，本发明包括具有随机存取存储器，第一接口和第二接口的装置。第一接口耦合在随机存取存储器和多个存储设备之间，并且以先进先出（FIFO）的方式操作。第二接口耦合在随机存取存储器和处理器之间，并以随机存取方式操作。结果，当在随机存取存储器和存储设备之间传送数据时，处理器不需要处于循环中。

36. 发明授权

US08494059B1 Buffer controller 有权
标题翻译：缓冲控制器
公开(公告)号：US08494059B1
公开(公告)日：2013-07-23
申请号：US12511425
申请日：2009-07-29
申请人： Hongjie Guan , Junqiang Lan , Yaojun Luo , Guan-Ming Su , Ching-Han Tsai , Chi-Kuang Chen , Li Sha
发明人： Hongjie Guan , Junqiang Lan , Yaojun Luo , Guan-Ming Su , Ching-Han Tsai , Chi-Kuang Chen , Li Sha
IPC分类号： H04N11/02
CPC分类号： H04N19/423 , H04N19/44 , H04N19/91
摘要： Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.
摘要翻译：描述了与缓冲器控制器相关联的设备，系统，方法和其他实施例。在一个实施例中，装置包括缓冲器以缓冲数据。该装置还包括状态寄存器和控制逻辑。控制逻辑至少处理写命令。当缓冲区已满并且写入数据到缓冲区的写入命令被接收时，控制逻辑被配置为：接收数据而不将数据写入缓冲器，发送缓冲区被写入的确认，并设置溢出位在状态寄存器中。

37. 发明授权

US08363729B1 Visual data compression algorithm with parallel processing capability 有权
公开(公告)号：US08363729B1
公开(公告)日：2013-01-29
申请号：US12612836
申请日：2009-11-05
申请人： Li Sha , Haohong Wang , Leung Chung Lai , Tzun Wei Lee
发明人： Li Sha , Haohong Wang , Leung Chung Lai , Tzun Wei Lee
IPC分类号： H04N7/26
CPC分类号： H04N19/18 , H04N19/1887 , H04N19/436 , H04N19/60 , H04N19/91
摘要： Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

38. 发明授权

US08127058B1 System and method of video decoding using hybrid buffer 有权
公开(公告)号：US08127058B1
公开(公告)日：2012-02-28
申请号：US12509800
申请日：2009-07-27
申请人： Li Sha , Ching-Han Tsai , Chengjun Wang
发明人： Li Sha , Ching-Han Tsai , Chengjun Wang
IPC分类号： G06F3/00
CPC分类号： H04N19/433 , G06F5/065 , H04N19/426 , H04N19/44
摘要： In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

39. 发明申请

US20090268086A1 METHOD AND SYSTEM FOR SCALING, FILTERING, SCAN CONVERSION, PANORAMIC SCALING, YC ADJUSTMENT, AND COLOR CONVERSION IN A DISPLAY CONTROLLER 审中-公开
标题翻译：在显示控制器中进行缩放，过滤，扫描转换，全景缩放，YC调整和颜色转换的方法和系统
公开(公告)号：US20090268086A1
公开(公告)日：2009-10-29
申请号：US12189721
申请日：2008-08-11
申请人： Yu T. Tian , Qifan Huang , Li Sha
发明人： Yu T. Tian , Qifan Huang , Li Sha
IPC分类号： H04N7/01
CPC分类号： G06T3/4084 , G06T5/20 , G06T2200/28
摘要： Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.
摘要翻译：公开了用于执行全景缩放的技术，其减少全景图像中的可见失真。此外，公开了用于执行组合YC调整和颜色转换的技术，通过减少当将YC调整和颜色转换实现为单独操作时所需的逻辑门数和存储缓冲器的数量来减小视频操纵硬件的尺寸和功率要求。

40. 发明授权

US07432988B2 Address generation for video processing 失效
标题翻译：视频处理地址生成
公开(公告)号：US07432988B2
公开(公告)日：2008-10-07
申请号：US11710772
申请日：2007-02-26
申请人： Shuhua Xiang , Hongjun Yuan , Li Sha
发明人： Shuhua Xiang , Hongjun Yuan , Li Sha
IPC分类号： H04N9/64
CPC分类号： H04N19/20 , G06T1/60 , H04N5/14 , H04N19/423
摘要： A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
摘要翻译：视频处理系统包括输入和输出地址发生器。地址发生器能够生成与要从设备读取和写入的数据相关联的线性地址。线性地址被转换为随机地址，使得可以从设备读取与宏块相关联的数据并将其写入设备。

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