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31. 发明申请

US20080164512A1 LIGHT ERASABLE MEMORY AND METHOD THEREFOR 有权
标题翻译：光可擦除存储器及其方法
公开(公告)号：US20080164512A1
公开(公告)日：2008-07-10
申请号：US11620075
申请日：2007-01-05
申请人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
发明人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译：半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。互连层在半导体层之上。存储器阵列位于顶部半导体层部分和互连层的一部分中。通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。结果是存储器阵列从背面接收光并被擦除。

32. 发明申请

US20070082495A1 Semiconductor device having nano-pillars and method therefor 有权
标题翻译：具有纳米柱的半导体器件及其方法
公开(公告)号：US20070082495A1
公开(公告)日：2007-04-12
申请号：US11244516
申请日：2005-10-06
申请人： Leo Mathew , Rajesh Rao , Ramachandran Muralidhar
发明人： Leo Mathew , Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L29/76 , H01L21/461 , H01L21/302 , H01L29/745
CPC分类号： H01L29/42368 , B82Y10/00 , H01L21/28273 , H01L21/32139 , H01L28/91 , H01L29/512 , H01L29/513
摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.
摘要翻译：半导体器件包括由导电材料形成的多个支柱。通过使用多个纳米晶体作为用于图案化导电材料的硬掩模来形成柱。导电材料的厚度决定了支柱的高度。同样，柱的宽度由纳米晶体的直径决定。在一个实施例中，柱由多晶硅形成，并且用作具有良好电荷保持和低电压操作的非易失性存储单元的电荷存储区。在另一个实施例中，支柱由金属形成，并且用作具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器的平板电极，而不增加集成电路的表面积。

33. 发明申请

US20060220102A1 Non-volatile memory cell including a capacitor structure and processes for forming the same 有权
标题翻译：包括电容器结构的非易失性存储单元及其形成方法
公开(公告)号：US20060220102A1
公开(公告)日：2006-10-05
申请号：US11083878
申请日：2005-03-18
申请人： Leo Mathew , Ramachandran Muralidhar , Tab Stephens
发明人： Leo Mathew , Ramachandran Muralidhar , Tab Stephens
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.
摘要翻译：非易失性存储单元可以包括衬底，覆盖衬底的有源区和覆盖衬底的电容器结构。从平面图，电容器结构围绕有源区域。在一个实施例中，非易失性存储单元包括浮置栅电极和控制栅电极。电容器结构包括第一电容器部分，第一电容器部分包括第一电容器电极和第二电容器电极。第一电容器电极电连接到浮置栅电极，并且第二电容器电极电连接到控制栅电极。用于形成非易失性存储单元的方法可以包括在衬底上形成有源区，并在衬底上形成电容器结构，其中从平面图看，电容器结构围绕有源区。

34. 发明申请

US20050282345A1 Transistor with vertical dielectric structure 有权
标题翻译：具有垂直电介质结构的晶体管
公开(公告)号：US20050282345A1
公开(公告)日：2005-12-22
申请号：US10871772
申请日：2004-06-18
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/7887
摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.
摘要翻译：一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。半导体结构包括沟道区（731）和源极/漏极区（707,709）。晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

35. 发明授权

US06967143B2 Semiconductor fabrication process with asymmetrical conductive spacers 失效
公开(公告)号：US06967143B2
公开(公告)日：2005-11-22
申请号：US10427141
申请日：2003-04-30
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

36. 发明申请

US20050098822A1 Transistor having three electrically isolated electrodes and method of formation 有权
标题翻译：具有三个电隔离电极的晶体管和形成方法
公开(公告)号：US20050098822A1
公开(公告)日：2005-05-12
申请号：US10705317
申请日：2003-11-10
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/788 , H01L29/76
CPC分类号： H01L27/108 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881
摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
摘要翻译：晶体管（10）形成有三个可分别控制的栅极（44,42,18）。三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。通道侧壁上的电介质可以不同于通道顶部的电介质。选择性地制造到源极，漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

37. 发明申请

US20100227475A1 METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE 审中-公开
标题翻译：使用分离技术形成电子设备的方法
公开(公告)号：US20100227475A1
公开(公告)日：2010-09-09
申请号：US12784984
申请日：2010-05-21
申请人： Leo Mathew , Dharmesh Jawarani
发明人： Leo Mathew , Dharmesh Jawarani
IPC分类号： H01L21/44
CPC分类号： H01L21/26506 , H01L31/022425 , H01L31/028 , H01L31/0304 , H01L31/0312 , H01L31/03682 , H01L31/03762 , H01L31/03765 , H01L31/068 , H01L31/1864 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed.
摘要翻译：形成电子器件的方法可以包括通过电化学工艺在包括半导体材料的衬底的侧面上形成金属层。该方法还可以包括在距离侧面一定距离处将分离增强物质引入衬底中，并且将半导体层和金属层与衬底分离，其中半导体层是衬底的一部分。在一个具体的实施方案中，分离增强物质可以结合到金属层中并移动到基底中，并且在具体实施方案中，可以将分离增强物质注入到基底中。在另一个实施例中，可以使用这两种技术。在另一实施例中，可以执行双面处理。

38. 发明授权

US07709303B2 Process for forming an electronic device including a fin-type structure 有权
标题翻译：用于形成包括翅片型结构的电子设备的方法
公开(公告)号：US07709303B2
公开(公告)日：2010-05-04
申请号：US11328668
申请日：2006-01-10
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.
摘要翻译：用于形成电子器件的工艺可以包括形成用于鳍型结构的第一高度的半导体鳍片，并且去除半导体鳍片的一部分，使得半导体鳍片缩短到第二高度。根据具体实施例，可以形成第二半导体鳍片，第一和第二半导体鳍片中的每一个具有表示沟道宽度的不同高度。根据另一具体实施例，可以形成第二和第三半导体鳍片，第一，第二和第三半导体鳍片中的每一个具有代表沟道宽度的不同高度。

39. 发明授权

US07432122B2 Electronic device and a process for forming the electronic device 有权
标题翻译：电子设备和用于形成电子设备的过程
公开(公告)号：US07432122B2
公开(公告)日：2008-10-07
申请号：US11327686
申请日：2006-01-06
申请人： Leo Mathew , Michael G. Khazhinsky
发明人： Leo Mathew , Michael G. Khazhinsky
IPC分类号： H01L21/00 , H01L21/84 , H01L21/20 , H01L21/36
CPC分类号： H01L27/0811 , H01L29/0657 , H01L29/42312 , H01L29/7391 , H01L29/785
摘要： An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.
摘要翻译：电子设备可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。与结点隔开并相邻的第一导电构件可连接到第一信号线。与结点间隔开并与其相邻的第二导电构件可以电连接到第二信号线并与第一导电构件电绝缘。结二极管结构可以包括p-n或p-i-n结。还描述了用于形成电子设备的过程。

40. 发明授权

US07301741B2 Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit 有权
标题翻译：具有多个独立栅极场效应晶体管（MIGFET）导轨钳位电路的集成电路
公开(公告)号：US07301741B2
公开(公告)日：2007-11-27
申请号：US11130873
申请日：2005-05-17
申请人： Michael G. Khazhinsky , Leo Mathew
发明人： Michael G. Khazhinsky , Leo Mathew
IPC分类号： H02H3/22
CPC分类号： H01L27/0251 , H01L27/0292 , H01L29/7855
摘要： A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled between the first (112) and second (114) power supply voltage rails, and first and second gates. The ESD event detector circuit (138) is coupled between the first (112) and second (114) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first (112) and second (114) power supply voltage rails, the ESD event detector circuit (138) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET (128) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET (128) conductive with relatively high conductivity.
摘要翻译：轨道钳位电路（100）包括第一和第二电源电压轨道，多个独立的栅极场效应晶体管（MIGFET）（128）和ESD事件检测器电路（138）。 MIGFET（128）具有耦合在第一（112）和第二（114）电源电压轨道之间的源极/漏极路径，以及第一和第二栅极。 ESD事件检测器电路（138）耦合在第一（112）和第二（114）电源电压轨道之间，并且具有分别耦合到MIGFET的第一和第二栅极的第一和第二输出端子。响应于第一（112）和第二（114）电源电压轨道之间的静电放电（ESD）事件，ESD事件检测器电路（138）向第二栅极提供电压以降低MIGFET的绝对阈值电压（128），同时向第一栅极提供高于绝对阈值电压的电压，从而使MIGFET（128）具有较高导电性的导电性。

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