专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20060198216A1 Memory array architecture for a memory device and method of operating the memory array architecture 有权
标题翻译：用于存储器件的存储器阵列架构和操作存储器阵列架构的方法
公开(公告)号：US20060198216A1
公开(公告)日：2006-09-07
申请号：US11371051
申请日：2006-03-07
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/0458 , G11C16/08 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.
摘要翻译：本发明的高集成度存储器阵列架构包括存储单元阵列，其包括以预定配置布置的存储单元，以及具有不同阈值电压的选择晶体管，以便选择存储单元阵列的存储器串。通过向选择晶体管施加适当的偏置电压，可以选择特定的存储器串，使得可以执行存储器阵列的操作而不与相邻的存储器单元进行干预。

32. 发明申请

US20110280066A1 SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT SOURCE/DRAIN REGION 有权
标题翻译：具有场效应源/漏区的半导体器件
公开(公告)号：US20110280066A1
公开(公告)日：2011-11-17
申请号：US13192798
申请日：2011-07-28
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： G11C11/34 , H01L27/105
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

33. 发明授权

US07623366B2 Semiconductor device having a field effect source/drain region 有权
标题翻译：具有场效应源极/漏极区域的半导体器件
公开(公告)号：US07623366B2
公开(公告)日：2009-11-24
申请号：US11643022
申请日：2006-12-20
申请人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
发明人： Ki-Tae Park , Jung-Dal Choi , Uk-Jin Roh
IPC分类号： G11C5/06 , G11C11/34 , G11C16/04 , H01L29/80 , H01L21/337
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/42332 , H01L29/792
摘要： A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.
摘要翻译：半导体器件包括限定在半导体衬底中的有源区和跨过有源区的栅电极。源/漏区限定在栅电极两侧的有源区中。源极/漏极区域中的至少一个是由栅极的边缘场产生的场效应源极/漏极区域。另一个源极/漏极区是具有与衬底不同的杂质场和不同导电率的PN结源极/漏极区。源极/漏极区域中的至少一个是场效应源极/漏极区域。因此，在设备中减少或消除短的通道效应。

34. 发明申请

US20080266952A1 MEMORY ARRAY ARCHITECTURE FOR A MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY ARRAY ARCHITECTURE 有权
标题翻译：用于存储器件的存储器阵列架构和操作存储器阵列架构的方法
公开(公告)号：US20080266952A1
公开(公告)日：2008-10-30
申请号：US12166246
申请日：2008-07-01
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/0458 , G11C16/08 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.
摘要翻译：本发明的高集成度存储器阵列架构包括存储单元阵列，其包括以预定配置布置的存储单元，以及具有不同阈值电压的选择晶体管，以便选择存储单元阵列的存储器串。通过向选择晶体管施加适当的偏置电压，可以选择特定的存储器串，使得可以执行存储器阵列的操作而不与相邻的存储器单元进行干预。

35. 发明授权

US07408806B2 Memory array architecture for a memory device and method of operating the memory array architecture 有权
标题翻译：用于存储器件的存储器阵列架构和操作存储器阵列架构的方法
公开(公告)号：US07408806B2
公开(公告)日：2008-08-05
申请号：US11371051
申请日：2006-03-07
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/0458 , G11C16/08 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/7923
摘要： A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.
摘要翻译：本发明的高集成度存储器阵列架构包括存储单元阵列，其包括以预定配置布置的存储单元，以及具有不同阈值电压的选择晶体管，以便选择存储单元阵列的存储器串。通过向选择晶体管施加适当的偏置电压，可以选择特定的存储器串，使得可以执行存储器阵列的操作而不与相邻的存储器单元进行干预。

36. 发明申请

US20070210372A1 MEMORY CELL ARRAY STRUCTURES IN NAND FLASH MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译： NAND闪存存储器件中的存储单元阵列结构及其制造方法
公开(公告)号：US20070210372A1
公开(公告)日：2007-09-13
申请号：US11617233
申请日：2006-12-28
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND-type non-volatile semiconductor memory device includes a gate insulating layer on an active region of a semiconductor substrate, first and second select gate structures on the active region, and a memory gate structure therebetween. The first and second select gate structures respectively include a plurality of select gate patterns, and the memory gate structure includes a plurality of storage gate patterns. The gate insulating layer includes a plurality of openings therein exposing portions of the active region between ones of the plurality of select gate patterns of the first and second select gate structures. The device may further include impurity regions in portions of the active region between the gate patterns, and halo regions adjacent ones of the impurity regions in the portions of the active region exposed by the openings in the gate insulating layer. Related fabrication methods are also discussed.
摘要翻译： NAND型非易失性半导体存储器件包括在半导体衬底的有源区上的栅极绝缘层，有源区上的第一和第二选择栅极结构以及它们之间的存储栅结构。第一和第二选择栅极结构分别包括多个选择栅极图案，并且存储器栅极结构包括多个存储栅极图案。栅极绝缘层包括多个开口，其中将有源区域的部分暴露在第一和第二选择栅极结构的多个选择栅极图案之间。该器件还可以包括位于栅极图案之间的有源区域的部分中的杂质区域和与栅极绝缘层中的开口暴露的有源区域的部分中的杂质区域相邻的晕圈区域。还讨论了相关的制造方法。

37. 发明申请

US20070195610A1 Flash memory devices, methods of erasing flash memory devices and memory systems including the same 有权
标题翻译：闪存设备，擦除闪存设备的方法和包括其的存储器系统
公开(公告)号：US20070195610A1
公开(公告)日：2007-08-23
申请号：US11704343
申请日：2007-02-09
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483
摘要： In a method of erasing a non-volatile memory device an electric field is applied between a plurality of word lines and a substrate to erase memory cells in a memory block simultaneously. After a first time period elapses, the electric field applied between a first portion of the plurality of word lines and the substrate is maintained to erase memory cells, while the electric field between a second portion of the plurality of word lines and the substrate is removed or reduced.
摘要翻译：在擦除非易失性存储器件的方法中，在多个字线和衬底之间施加电场以同时擦除存储器块中的存储器单元。在经过第一时间段之后，保持施加在多个字线的第一部分和基板之间的电场以擦除存储单元，同时多个字线的第二部分与基板之间的电场被去除或减少。

38. 发明申请

US20060239077A1 NAND Flash Memory Device Having Dummy Memory cells and Methods of Operating Same 有权
标题翻译：具有虚拟存储器单元的NAND闪存器件和操作方法相同
公开(公告)号：US20060239077A1
公开(公告)日：2006-10-26
申请号：US11279607
申请日：2006-04-13
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

39. 发明申请

US20060180847A1 Two-bit non-volatile memory devices including independently-controllable gate electrodes and methods for fabricating the same 审中-公开
标题翻译：包括可独立控制的栅电极的两位非易失性存储器件及其制造方法
公开(公告)号：US20060180847A1
公开(公告)日：2006-08-17
申请号：US11353726
申请日：2006-02-14
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/513 , H01L29/66833 , H01L29/7923
摘要： A non-volatile integrated circuit memory device includes a substrate including first and second source/drain regions therein and a channel region therebetween, a first memory cell on the channel region adjacent the first source/drain region, and a second memory cell on the channel region adjacent the second source/drain region. The first memory cell includes a first conductive gate on the channel region and a first multi-layered charge storage structure therebetween. Similarly, the second memory cell includes a second conductive gate on the channel region and a second multi-layered charge storage structure therebetween. A single-layer insulating layer on the channel region extends between the first and second memory cells along sidewalls thereof. The single-layer insulating layer may not include a charge-trapping layer, and may separate the first and second conductive gates by a distance of less than a thickness of the first multi-layered charge storage structure. Related fabrication methods are also discussed.
摘要翻译：非易失性集成电路存储器件包括其中包括第一和第二源极/漏极区域和其间的沟道区域的衬底，与第一源极/漏极区域相邻的沟道区域上的第一存储单元，以及沟道上的第二存储器单元区域与第二源极/漏极区域相邻。第一存储单元包括沟道区上的第一导电栅极和它们之间的第一多层电荷存储结构。类似地，第二存储单元包括沟道区上的第二导电栅极和它们之间的第二多层电荷存储结构。沟道区上的单层绝缘层沿其侧壁在第一和第二存储单元之间延伸。单层绝缘层可以不包括电荷捕获层，并且可以将第一和第二导电栅极分开小于第一多层电荷存储结构的厚度的距离。还讨论了相关的制造方法。

40. 发明申请

US20150214478A1 VARIABLE RESISTANCE MEMORY DEVICES 有权
标题翻译：可变电阻存储器件
公开(公告)号：US20150214478A1
公开(公告)日：2015-07-30
申请号：US14457439
申请日：2014-08-12
申请人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
发明人： Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/08 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
摘要翻译：可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。第一导线沿第一方向延伸。第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。存储单元包括可变电阻器件。存储单元位于第一导线和第二导线的交叉区域。第一气隙在存储单元之间沿第一方向延伸。第二气隙沿第二方向在存储单元之间延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式