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31. 发明授权

US08735962B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08735962B2
公开(公告)日：2014-05-27
申请号：US13599680
申请日：2012-08-30
申请人： Sung Jin Whang , Dong Sun Sheen , Seung Ho Pyi , Min Soo Kim
发明人： Sung Jin Whang , Dong Sun Sheen , Seung Ho Pyi , Min Soo Kim
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11556 , H01L29/7889
摘要： A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.
摘要翻译：根据本发明的实施例的半导体器件包括从半导体衬底向上突出的垂直沟道层，覆盖垂直沟道层的侧壁的隧道绝缘层，彼此分离并堆叠的多个浮动栅极沿着垂直沟道层，并且在其间插入隧道绝缘层的周围的垂直沟道层，分别包围多个浮置栅极的多个控制栅极和设置在多个控制栅极之间的层间绝缘层。

32. 发明申请

US20110193154A1 Non-volatile Memory Device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110193154A1
公开(公告)日：2011-08-11
申请号：US13089865
申请日：2011-04-19
申请人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Yong Soo Kim
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.
摘要翻译：非易失性存储器件包括衬底，衬底上的隧道层，在隧穿层上方包括氮化物层和氮化硼氮化物层的电荷俘获层，以及电荷俘获层上的阻挡层，以及控制栅极电极布置在阻挡层上。

33. 发明授权

US07242075B2 Silicon wafers and method of fabricating the same 有权
标题翻译：硅晶片及其制造方法
公开(公告)号：US07242075B2
公开(公告)日：2007-07-10
申请号：US10699438
申请日：2003-10-31
申请人： Young Hee Mun , Kun Kim , Chung Geun Koh , Seung Ho Pyi
发明人： Young Hee Mun , Kun Kim , Chung Geun Koh , Seung Ho Pyi
IPC分类号： H01L29/32
CPC分类号： H01L21/324 , H01L21/3225
摘要： By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
摘要翻译：通过使用两步RTP（快速热处理）工艺，提供晶片，其具有通过控制位于晶片表面区域上的精细氧沉淀物和OiSF（氧化诱导堆叠故障）而固定的理想半导体器件区域。通过执行所公开的两步快速热处理，可以精确地控制缺陷的分布，并且可以形成理想的器件有源区至距离晶片表面一定距离。此外，通过使晶体的内部区域即体积区域中的氧析出物和体积堆垛层错能够在深度方向上具有恒定的密度，可以使内部吸气（IG）效率最大化。为了获得体积区域中的氧沉淀物的恒定浓度分布和体积堆垛层错，将晶片在预定的混合气体气氛中进行前述的两步快速热处理。

34. 发明授权

US06841461B2 Method for forming gate electrode of semiconductor device 失效
标题翻译：形成半导体器件栅电极的方法
公开(公告)号：US06841461B2
公开(公告)日：2005-01-11
申请号：US10701327
申请日：2003-11-04
申请人： Seung Ho Pyi
发明人： Seung Ho Pyi
IPC分类号： H01L21/336 , H01L21/265 , H01L21/266 , H01L21/28 , H01L21/3215 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/3205
CPC分类号： H01L21/28247 , H01L21/26506 , H01L21/266 , H01L21/28061 , H01L21/32155 , H01L29/4941
摘要： Disclosed is a method for a gate electrode of a semiconductor device, which forms a re-oxidation film of a sufficient thickness by a low temperature re-oxidation process. Gate oxide film, doped-silicon film, tungsten nitride film, tungsten film, and hard mask film are sequentially formed on semiconductor substrate. Hard mask film is patterned. Tungsten film and tungsten nitride film are etched using patterned hard mask film as an etching barrier in order to expose doped-silicon film. Predetermined oxidation-accelerating ions are implanted into a portion and a side of exposed doped-silicon film. A portion of exposed doped-silicon film is etched. Substrate resulting object is re-oxidized to form a re-oxidation film at a side of etched doped-silicon film.
摘要翻译：公开了半导体器件的栅电极的方法，其通过低温再氧化工艺形成足够厚度的再氧化膜。栅极氧化膜，掺杂硅膜，氮化钨膜，钨膜和硬掩模膜依次形成在半导体衬底上。硬掩模膜被图案化。使用图案化的硬掩模膜作为蚀刻阻挡层来蚀刻钨膜和氮化钨膜，以暴露掺杂硅膜。将预定的氧化促进离子注入暴露的掺杂硅膜的一部分和一侧。暴露的掺杂硅膜的一部分被蚀刻。将底物产生的物体再次氧化，以在蚀刻的掺杂硅膜的一侧形成再氧化膜。

35. 发明授权

US06776841B2 Method for fabricating a semiconductor epitaxial wafer having doped carbon and a semiconductor epitaxial wafer 失效
标题翻译：制造具有掺杂碳的半导体外延晶片和半导体外延晶片的方法
公开(公告)号：US06776841B2
公开(公告)日：2004-08-17
申请号：US10034221
申请日：2001-12-28
申请人： Seung Ho Pyi
发明人： Seung Ho Pyi
IPC分类号： C30B1504
CPC分类号： C30B29/06 , C30B13/10 , C30B15/04 , H01L29/1033 , H01L29/16
摘要： A method of fabricating a semiconductor epitaxial wafer having doped carbon includes the steps of mixing a quantity of carbon with a quantity of silicon and then melting together the quantities of carbon and silicon, growing an ingot with carbon from the melted silicon containing carbon, grinding the ingot having carbon so as to produce a flat surface and a notch, slicing the ingot having carbon into a piece of silicon wafer, polishing the silicon wafer having carbon, and growing an epitaxial silicon layer on a surface of the polished silicon wafer having carbon.
摘要翻译：制造具有掺杂碳的半导体外延晶片的方法包括以下步骤：将一定量的碳与一定数量的硅混合，然后将碳和硅的量一起熔化，从熔融的含硅碳中生长碳块，研磨具有碳以便产生平坦表面和凹口的锭，将具有碳的锭切割成一块硅晶片，抛光具有碳的硅晶片，以及在具有碳的抛光的硅晶片的表面上生长外延硅层。

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