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31. 发明授权

US09287136B2 FinFET field-effect transistors with atomic layer doping 有权
标题翻译：具有原子层掺杂的FinFET场效应晶体管
公开(公告)号：US09287136B2
公开(公告)日：2016-03-15
申请号：US13606873
申请日：2012-09-07
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L27/088 , H01L21/20 , H01L21/24 , H01L21/314 , H01L21/02 , H01L29/36 , H01L21/225 , H01L29/66 , H01L29/165
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
摘要翻译：公开了使用原子层掺杂工艺制造的场效应晶体管。根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

32. 发明授权

US08586441B1 Germanium lateral bipolar junction transistor 有权
标题翻译：锗横向双极结晶体管
公开(公告)号：US08586441B1
公开(公告)日：2013-11-19
申请号：US13611606
申请日：2012-09-12
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要翻译：使用绝缘体上的锗（GOI）衬底形成锗横向双极结型晶体管（BJT）。在GOI衬底的锗层的顶表面上沉积硅钝化层。随后形成浅沟槽隔离结构，非本征基区结构和基底间隔物。通过离子注入在锗层内形成锗发射极区，锗基区和锗集电极区。在硅钝化层中形成硅发射极区域，硅基区域和硅集电极区域。在可选地形成发射极接触区域和集电极接触区域之后，可以形成金属半导体合金区域。在硅基区和锗基区之间以及硅发射极区和锗发射极区之间提供少量载流子的宽间隙接触。

33. 发明授权

US08551845B2 Structure and method for increasing strain in a device 有权
标题翻译：增加器件应变的结构和方法
公开(公告)号：US08551845B2
公开(公告)日：2013-10-08
申请号：US12886903
申请日：2010-09-21
申请人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
发明人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26566 , H01L21/26593 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
摘要翻译：公开了用于增加器件中应变的方法和结构，特别是n型场效应晶体管（NFET）互补金属氧化物半导体（CMOS）器件。本发明的实施例包括生长外延层，进行冷碳或簇碳预非晶化注入以将取代碳注入到外延层中，在外延层上形成拉伸帽，然后退火以使非晶层重结晶以产生应力记忆技术（SMT）效应。因此，外延层将包括取代碳并具有由SMT引起的记忆拉伸应力。本发明的实施例还可以包括在外延层下面的下部外延层，下部外延层包括例如硅碳磷（SiCP）层。

34. 发明授权

US08716096B2 Self-aligned emitter-base in advanced BiCMOS technology 失效
标题翻译：先进的BiCMOS技术中的自对准发射极基极
公开(公告)号：US08716096B2
公开(公告)日：2014-05-06
申请号：US13323977
申请日：2011-12-13
申请人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
发明人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/737 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
摘要翻译：公开了一种自对准双极晶体管及其制造方法。在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。形成第一开口，暴露外部基底的表面的一部分。在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

35. 发明授权

US08603883B2 Interface control in a bipolar junction transistor 失效
标题翻译：双极结晶体管中的接口控制
公开(公告)号：US08603883B2
公开(公告)日：2013-12-10
申请号：US13297464
申请日：2011-11-16
申请人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
发明人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , G06F17/5045 , H01L29/1004 , H01L29/66272 , H01L29/7371
摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
摘要翻译：制造双极结型晶体管，双极结型晶体管以及双极结型晶体管的设计结构的方法。本征基底层的第一部分被掩蔽，同时蚀刻本征基底层的第二部分。作为掩蔽的结果，本征基底层的第二部分比本征基底层的第一部分薄。在与本征基层的第一和第二部分分别的接触关系中形成发射极和非本征基层。

36. 发明申请

US20130119442A1 JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY 有权
标题翻译：具有选择性外延形成的上升源和漏区的连接场效应晶体管
公开(公告)号：US20130119442A1
公开(公告)日：2013-05-16
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , G06F17/50 , H01L29/808
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

37. 发明申请

US20120289018A1 SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译： SOI SiGe-BASE横向双极晶体管晶体管
公开(公告)号：US20120289018A1
公开(公告)日：2012-11-15
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

38. 发明授权

US08198673B2 Asymmetric epitaxy and application thereof 有权
标题翻译：不对称外延及其应用
公开(公告)号：US08198673B2
公开(公告)日：2012-06-12
申请号：US13080702
申请日：2011-04-06
申请人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
发明人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成栅极结构，该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物，并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

39. 发明申请

US20110171788A1 Fabrication of Field Effect Devices Using Spacers 失效
标题翻译：使用Spacers制造场效应器件
公开(公告)号：US20110171788A1
公开(公告)日：2011-07-14
申请号：US12684997
申请日：2010-01-11
申请人： Kevin K. Chan , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/6656 , H01L29/66772
摘要： A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.
摘要翻译：一种形成场效应器件的方法包括在绝缘体上硅层（SOI）上形成栅极部分，在邻近栅极部分的SOI层上形成第一间隔元件，在SOI层上沉积间隔物材料层，第一隔离构件和栅极部分，去除间隔物材料层的部分，以在与第一间隔件相邻的SOI层上形成第二间隔件，通过将离子注入到SOI层上形成源极区域和漏极区域 SOI层，并蚀刻以除去第二间隔件。

40. 发明授权

US07888264B2 MOSFET structure with multiple self-aligned silicide contacts 有权
标题翻译：具有多个自对准硅化物触点的MOSFET结构
公开(公告)号：US07888264B2
公开(公告)日：2011-02-15
申请号：US12814942
申请日：2010-06-14
申请人： Kevin K. Chan , Christian Lavoie , Kern Rim
发明人： Kevin K. Chan , Christian Lavoie , Kern Rim
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

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