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31. 发明授权

US08086783B2 High availability memory system 有权
标题翻译：高可用性内存系统
公开(公告)号：US08086783B2
公开(公告)日：2011-12-27
申请号：US12390731
申请日：2009-02-23
申请人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
发明人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F11/1004 , G06F12/0886
摘要： A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
摘要翻译：提供了高可用性的内存系统。存储器系统包括多个存储器通道。每个存储器通道包括至少一个存储器模块，其中存储器件被组织为耦合到存储器设备总线段的部分等级。每个部分等级包括作为存储器设备总线段的子集上的子信道可访问的存储器件的子集。存储器系统还包括与多个存储器通道通信的存储器控制器。存储器控制器通过存储器通道分配访问请求以访问完整等级。完整等级包括在独立内存通道上的至少两个部分等级。可以同时访问公共内存模块上的部分排名。存储器模块可以在至少两个可同时访问的部分等级之间使用至少一个校验和存储器设备作为专用校验和存储器设备或共享校验和存储器设备。

32. 发明授权

US07925826B2 System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency 失效
标题翻译：通过允许存储器通道以独立于存储器件频率的频率工作来增加存储器通道的总体带宽的系统
公开(公告)号：US07925826B2
公开(公告)日：2011-04-12
申请号：US12019095
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth, which is independent of the second operating frequency.
摘要翻译：提供了一种存储器系统，其通过以独立频率操作存储器通道来增加存储器通道的总体带宽。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。使用异步边界，存储通道以最大设计的工作带宽运行，独立于第二个工作频率。

33. 发明授权

US07895374B2 Dynamic segment sparing and repair in a memory system 失效
标题翻译：内存系统中的动态段保存和修复
公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

34. 发明申请

US20110004709A1 Method for Enhancing the Memory Bandwidth Available Through a Memory Module 失效
标题翻译：通过内存模块提高内存带宽的方法
公开(公告)号：US20110004709A1
公开(公告)日：2011-01-06
申请号：US11850190
申请日：2007-09-05
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F3/00 , G06F12/06
CPC分类号： G06F13/1684
摘要： A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
摘要翻译：提供了一种用于增强通过存储器系统的存储器模块可用的存储器带宽的方法。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器系统包括集成在存储器集线器设备中的第一存储器设备数据接口，其与集成在存储器模块中的第一组存储器设备进行通信。存储器系统还包括集成在存储器集线器设备中的第二存储器设备数据接口，其与集成在存储器模块中的第二组存储器设备进行通信。在存储器系统中，第一组存储器件与第二组存储器件分开。在存储器系统中，第一和第二组存储器设备经由独立的第一和第二存储器件数据接口由存储器集线器设备进行通信。

35. 发明授权

US07863089B2 Planar array contact memory cards 有权
公开(公告)号：US07863089B2
公开(公告)日：2011-01-04
申请号：US11855325
申请日：2007-09-14
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/82
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

36. 发明申请

US20100269021A1 Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module 审中-公开
标题翻译：在内存模块的内存集线器中进行纠错操作的方法
公开(公告)号：US20100269021A1
公开(公告)日：2010-10-21
申请号：US11850353
申请日：2007-09-05
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10
摘要： A method is provided for performing error correction operations in a memory module. A memory hub device, which is integrated in the memory module, receives an access request for accessing a set of memory devices of the memory module coupled to the memory hub device. Data is transferred between a link interface of the memory hub device and the set of memory devices. Error correction logic, which is integrated in the memory hub device, performs one or more error correction operations on the data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data, via a memory channel between an external memory controller and the link interface, without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.
摘要翻译：提供了一种用于在存储器模块中进行纠错操作的方法。集成在存储器模块中的存储器集线器设备接收访问耦合到存储器集线器设备的存储器模块的一组存储器设备的访问请求。数据在存储器集线器设备的链路接口和存储器设备组之间传送。集成在存储器集线器装置中的纠错逻辑对在链路接口和存储器件集合之间传送的数据执行一个或多个纠错操作。存储器集线器设备经由外部存储器控制器和链路接口之间的存储器通道发送和接收数据，而没有任何纠错码，从而减少了存储器通道上使用的带宽量。

37. 发明申请

US20100220536A1 ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
标题翻译：具有降低功率的高级存储器件和改进的性能
公开(公告)号：US20100220536A1
公开(公告)日：2010-09-02
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译：一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及输出延迟时钟。输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

38. 发明授权

US07739633B2 Verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling system and program product 失效
标题翻译：通过关键资源调度系统和程序产品驱动的随机仿真验证高度优化的同步管道
公开(公告)号：US07739633B2
公开(公告)日：2010-06-15
申请号：US12043209
申请日：2008-03-06
申请人： Faisal A. Ahmad , Kevin C. Gower , Anish T. Patel
发明人： Faisal A. Ahmad , Kevin C. Gower , Anish T. Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.
摘要翻译：测试逻辑电路模型的模型。测试包括为逻辑电路模型生成有效的随机输入激励序列。列举关键资源需求，列举关键资源可用性，并根据资源可用性选择刺激序列并确定执行所述刺激序列的合法时间。这包括产生输入刺激序列的多个可能的组合并且生成关键资源要求的阵列表示。这些用于生成关键资源可用性的阵列表示。

39. 发明授权

US07669086B2 Systems and methods for providing collision detection in a memory system 有权
标题翻译：用于在存储器系统中提供碰撞检测的系统和方法
公开(公告)号：US07669086B2
公开(公告)日：2010-02-23
申请号：US11461933
申请日：2006-08-02
申请人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
发明人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
IPC分类号： G06F11/00
CPC分类号： G06F13/4239 , G06F9/52
摘要： Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.
摘要翻译：用于在包括用于存储和检索用于处理系统的数据的存储器系统的存储器系统中提供冲突检测的系统和方法。存储器系统包括用于监视用于检测资源调度冲突的一个或多个存储器资源的资源调度冲突逻辑。存储器系统还包括用于响应于检测到一个或多个存储器资源上的资源调度冲突而产生错误信号的错误报告逻辑。

40. 发明申请

US20100005345A1 BIT SHADOWING IN A MEMORY SYSTEM 失效
标题翻译：记忆系统中的位冲突
公开(公告)号：US20100005345A1
公开(公告)日：2010-01-07
申请号：US12165799
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率错误率在一段时间内。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

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