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31. 发明申请

US20130087859A1 Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure 有权
标题翻译：包括门结构在内的半导体器件中的碳植入工作功能调整
公开(公告)号：US20130087859A1
公开(公告)日：2013-04-11
申请号：US13253268
申请日：2011-10-05
申请人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
发明人： Yue Liang , Dechao Guo , William K. Henson , Shreesh Narasimha , Yanfeng Wang
IPC分类号： H01L21/266 , H01L27/092
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/823857 , H01L29/1054 , H01L29/517
摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.
摘要翻译：一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。还公开了形成上述装置的方法。

32. 发明授权

US07838908B2 Semiconductor device having dual metal gates and method of manufacture 有权
标题翻译：具有双金属栅极的半导体器件及其制造方法
公开(公告)号：US07838908B2
公开(公告)日：2010-11-23
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L27/10
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

33. 发明授权

US08507992B2 High-K metal gate CMOS 有权
标题翻译：高K金属门CMOS
公开(公告)号：US08507992B2
公开(公告)日：2013-08-13
申请号：US13048170
申请日：2011-03-15
申请人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
发明人： Renee T. Mo , Huiming Bu , Michael P. Chudzik , William K. Henson , Mukesh V. Khare , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.
摘要翻译：提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

34. 发明申请

US20120286374A1 HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF 失效
标题翻译：介电/硅基板界面上耐高氧氧化物生长的高K电介质栅结构及其制造方法
公开(公告)号：US20120286374A1
公开(公告)日：2012-11-15
申请号：US13556795
申请日：2012-07-24
申请人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/2822 , H01L29/4966 , H01L29/51 , H01L29/66575
摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.
摘要翻译：用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

35. 发明申请

US20110272779A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20110272779A1
公开(公告)日：2011-11-10
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

36. 发明申请

US20110248350A1 METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG) 有权
标题翻译：包括高介电常数门绝缘子和金属栅的晶体管中的工作功能工程的方法和结构（HKMG）
公开(公告)号：US20110248350A1
公开(公告)日：2011-10-13
申请号：US12757323
申请日：2010-04-09
申请人： Michael P. Chudzik , William K. Henson , Unoh Kwon
发明人： Michael P. Chudzik , William K. Henson , Unoh Kwon
IPC分类号： H01L27/092 , H01L21/28 , H01L29/78
CPC分类号： H01L21/28176 , H01L21/28079 , H01L21/823857 , H01L29/495 , H01L29/517 , H01L29/6659
摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.
摘要翻译：实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时在集成电路中; 防止阈值正确协调。

37. 发明申请

US20110227171A1 HIGH-K DIELECTRIC AND METAL GATE STACK WITH MINIMAL OVERLAP WITH ISOLATION REGION 有权
标题翻译：具有隔离区域的最小重叠的高K电介质和金属栅极堆叠
公开(公告)号：US20110227171A1
公开(公告)日：2011-09-22
申请号：US13150378
申请日：2011-06-01
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
IPC分类号： H01L29/51
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

38. 发明授权

US07943493B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07943493B2
公开(公告)日：2011-05-17
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

39. 发明申请

US20100330783A1 ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权
标题翻译：全自动充电式电熔炉和增强型流量分流器
公开(公告)号：US20100330783A1
公开(公告)日：2010-12-30
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

40. 发明申请

US20100258875A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20100258875A1
公开(公告)日：2010-10-14
申请号：US12823225
申请日：2010-06-25
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/088
CPC分类号： H01L21/823842
摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.
摘要翻译：半导体结构。半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

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