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    • 33. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07592232B2
    • 2009-09-22
    • US12144752
    • 2008-06-24
    • Tomoyuki Hirano
    • Tomoyuki Hirano
    • H01L21/8234
    • H01L21/28123H01L29/66545H01L29/6656H01L29/6659H01L29/66606H01L29/7833Y10S438/954
    • A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the second insulating film that remains, while planarizing the first insulating film and the second insulating film that remains, forming a gate electrode trench by removing the dummy gate electrode and the dummy gate insulating film, forming a gate insulating film, and forming a gate electrode, wherein a field effect transistor is formed by the method.
    • 一种制造半导体器件的方法,包括以下步骤:形成伪栅极绝缘膜和伪栅电极,形成源区和漏区,形成第一绝缘膜,形成第二绝缘膜,去除第二绝缘膜,同时去除 保留第一绝缘膜和第二绝缘膜,同时平坦化保留的第一绝缘膜和第二绝缘膜,通过去除伪栅电极和伪栅极绝缘膜形成栅极绝缘膜,形成栅极绝缘膜,形成栅极绝缘膜, 以及形成栅电极,其中通过该方法形成场效应晶体管。
    • 38. 发明授权
    • Method for forming capacitor
    • 电容器形成方法
    • US06818502B2
    • 2004-11-16
    • US10774213
    • 2004-02-06
    • Tomoyuki HiranoHayato Iwamoto
    • Tomoyuki HiranoHayato Iwamoto
    • H01L21302
    • H01L28/84H01L21/02068H01L27/10852H01L28/91
    • The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.
    • 本发明提供一种用于形成电容器的方法,该电容器能够在圆柱形底部电极的暴露表面的整个表面上形成HSG-Si。 在半导体衬底上的圆筒芯层上形成芯图案,并且形成非晶硅膜以覆盖芯图案。 除去气缸芯层上的非晶硅膜,使得非晶硅膜保留在芯图案的内壁上,并且在芯图案的内壁上形成包含非晶硅膜的底电极。 蚀刻除去作为芯图案的组分的圆筒芯层,然后蚀刻除去在底电极表面上产生的天然氧化物膜和作为底电极的成分的非晶硅表面层。 此后,在底电极的表面上形成HSG-Si。
    • 39. 发明授权
    • Solid-state imaging device having a vertical transistor with a dual polysilicon gate
    • 具有具有双多晶硅栅极的垂直晶体管的固态成像装置
    • US08952315B2
    • 2015-02-10
    • US12574494
    • 2009-10-06
    • Kazunobu OhtaTomoyuki Hirano
    • Kazunobu OhtaTomoyuki Hirano
    • H01L27/00H01L31/00H01L31/113H01L27/146H01L29/66
    • H01L27/14614H01L27/14634H01L27/14689H01L29/66666
    • A solid-state imaging device includes: a pixel part having a photoelectric conversion part photoelectrically converting incident light to obtain signal charge; and a peripheral circuit part formed on a periphery of the pixel part on a semiconductor substrate. The pixel part having a vertical transistor that reads out the signal charge from the photoelectric conversion part and a planar transistor that processes the signal charge read out by the vertical transistor. The vertical transistor has a groove part formed on the semiconductor substrate; a gate insulator film formed on an inner surface of the groove part; a conducting layer formed on a surface of the gate insulator film on the semiconductor substrate within and around the groove part; a filling layer filling an interior of the groove part via the gate insulator film and the conducting layer; and an electrode layer connected to the conducting layer on the filling layer.
    • 一种固态成像装置,包括:像素部,具有光电转换部,对入射光进行光电转换,得到信号电荷; 以及形成在半导体衬底上的像素部分的周围的外围电路部分。 像素部分具有从光电转换部读出信号电荷的垂直晶体管和处理由垂直晶体管读出的信号电荷的平面晶体管。 垂直晶体管具有形成在半导体衬底上的沟槽部分; 形成在所述槽部的内表面上的栅极绝缘膜; 导电层,形成在所述半导体衬底的所述栅极绝缘膜的表面上,并且在所述沟槽部内和周围; 填充层,其经由所述栅极绝缘膜和所述导电层填充所述槽部的内部; 以及与填充层上的导电层连接的电极层。