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31. 发明专利

JP2012150033A Resistance measuring device and resistance measuring method 有权
标题翻译：电阻测量装置和电阻测量方法
公开(公告)号：JP2012150033A
公开(公告)日：2012-08-09
申请号：JP2011009602
申请日：2011-01-20
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： MIYAMOTO KENJI , ABE TAKAAKI , SHIMOIDA YOSHIO
IPC分类号： G01R27/02 , H01M10/04
CPC分类号： Y02E60/12
摘要： PROBLEM TO BE SOLVED: To provide a resistance measuring device and a resistance measuring method for accurately detecting resistance along a vertical direction to a surface of a resistance detection body.SOLUTION: A resistance measuring device 1 comprises: first current applying means 5 for applying a first current to first portions where resistance along a vertical direction to a surface of a resistance detection body 2 is to be measured; second current applying means 6 for applying a second current to second portions each set to surround the first portion and closer to an outer periphery than the first portion so as to make a potential difference between the first portions and the second portions along an in-plane direction of the resistance detection body 2 substantially zero; and first voltage detecting means 7 for detecting a first voltage obtained between the first portions in applying the first current and the second current.
摘要翻译：要解决的问题：提供一种电阻测量装置和用于精确地检测沿电阻检测体的表面的垂直方向的电阻的电阻测量方法。电阻测量装置1包括：第一电流施加装置5，用于向要测量电阻检测体2的表面的垂直方向的电阻施加第一电流; 第二电流施加装置6，用于将第二电流施加到第二部分，每个第二部分被设置为围绕第一部分并且比第一部分更靠近外周，以便沿着平面内的第一部分和第二部分之间形成电位差电阻检测体2的方向基本上为零; 以及第一电压检测装置7，用于在施加第一电流和第二电流时检测在第一部分之间获得的第一电压。版权所有（C）2012，JPO＆INPIT

32. 发明专利

JP2012069404A Electric device, gas discharging device for electric device and gas discharging method of electric device 有权
标题翻译：电气设备，用于电气设备的气体放电装置和电气设备的气体放电方法
公开(公告)号：JP2012069404A
公开(公告)日：2012-04-05
申请号：JP2010213629
申请日：2010-09-24
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： MUROYA YUJI , SHIMOIDA YOSHIO , OBIKA MOTOHARU , SATO MASANOBU , INOUE SHIHO , WATANABE SHIGEO
IPC分类号： H01M2/12 , H01M2/02
CPC分类号： Y02E60/12
摘要： PROBLEM TO BE SOLVED: To provide an electric device, a gas discharging device for an electric device and a gas discharging method of an electric device which can remove gas without decreasing electrolyte in the electric device when gas is generated in the electric device due to some factor.SOLUTION: The electric device comprises: a power generation element body which includes at least one electric cell 200; a jacket material 300 to house the power generation element body; a pipe 330 which is opened to the inside of the jacket material 300 at one end and provided with a cock 331 in the middle thereof; and a balloon 313 housed in a sealed case 11 which stores electrolyte inside where the other end of the pipe 330 is opened and expands when internal atmospheric pressure of the sealed case 11 decreases.
摘要翻译：要解决的问题：提供一种电气设备，用于电气设备的气体排出装置和电气设备的气体排出方法，当电气设备中产生气体时，可以在不减少电气设备中的电解液的情况下去除气体由于一些因素。解决方案：电气设备包括：发电元件主体，其包括至少一个电池200; 用于容纳发电元件主体的护套材料300; 管330，其在一端向套管材料300的内部开口并在其中间设置有旋塞331; 以及容纳在密封壳体11中的气囊313，其密封壳体11的内部空气压力下降时，存储电解液，其内部管330的另一端开放并膨胀。版权所有（C）2012，JPO＆INPIT

33. 发明专利

JP2011258435A Electrode for battery, electrode for bipolar battery and bipolar battery 审中-公开
标题翻译：电池用电极，双极电池和双极电池用电极
公开(公告)号：JP2011258435A
公开(公告)日：2011-12-22
申请号：JP2010132640
申请日：2010-06-10
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： SATO MASANOBU , HORIE HIDEAKI , AOYAGI AKINORI , SHIMOIDA YOSHIO , HOSAKA KENJI , MIYATAKE KAZUKI
IPC分类号： H01M4/13 , H01M4/02 , H01M4/66
CPC分类号： Y02E60/122
摘要： PROBLEM TO BE SOLVED: To provide an electrode for batteries capable of restricting a current from intensively flowing in a short circuit region even when an internal short circuit occurs, and capable of suppressing deterioration of durability of the electrode during charging and discharging.SOLUTION: The electrode for batteries has active material layers 13, 15 formed on the surface of a conductive collector 11. The active material layers 13, 15 are constituted by a plurality of divided active material parts 13a, 13b, 13c, ..., 15a, 15b, 15c, ... on that are divided, and ion conductive parts 13I, 15I for mutually connecting the divided active material parts.
摘要翻译：解决的问题：即使在发生内部短路的情况下，也能够提供一种能够限制电流在短路区域内集中流动的电池的电极，能够抑制充放电期间电极的耐久性劣化。解决方案：电池用电极具有形成在导电性集电体11的表面上的活性物质层13,15。活性物质层13,15由多个分割的活性物质部分13a，13b，13c构成。 ...，15a，15b，15c，...，以及用于相互连接分割的活性物质部分的离子传导部分13I，15I。版权所有（C）2012，JPO＆INPIT

34. 发明专利

JP2007335501A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007335501A
公开(公告)日：2007-12-27
申请号：JP2006163363
申请日：2006-06-13
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HOSHI MASAKATSU , SHIMOIDA YOSHIO , HAYASHI TETSUYA , TANAKA HIDEAKI
IPC分类号： H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce a leakage current during the off-state of a transistor without the deterioration of a current driving force. SOLUTION: A hetero semiconductor region 3 for hetero junction with an n-type drain region 2 formed on an n-type substrate region 1 is formed as a source region, a gate electrode 5 is formed via a gate insulating film 4 adjacent to the hetero junction between the drain region 2 and the hetero semiconductor region 3, and a driving point 9 of a field effect transistor is defined to a point where the gate insulating film 4, the hetero semiconductor region 3 and the drain region 2 are in contact with one another. In this field effect transistor, a p-type semiconductor region 10 is formed on the front surface of the drain region 2 around the periphery of the driving point 9 in contact with the driving point 9 of the transistor. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在晶体管的截止状态下减小漏电流，而不会导致电流驱动力的劣化。解决方案：形成用于与形成在n型衬底区域1上的n型漏极区域2的异质结的异质半导体区域3作为源极区域，栅极电极5经由邻近的栅极绝缘膜4形成到漏极区域2和异质半导体区域3之间的异质结，并且场效应晶体管的驱动点9被定义为栅极绝缘膜4，异质半导体区域3和漏极区域2处于彼此接触。在该场效应晶体管中，在驱动点9周围的漏极区域2的前表面上形成有与晶体管的驱动点9接触的p型半导体区域10。版权所有（C）2008，JPO＆INPIT

35. 发明专利

JP2007318092A Semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007318092A
公开(公告)日：2007-12-06
申请号：JP2007099076
申请日：2007-04-05
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HOSHI MASAKATSU , SHIMOIDA YOSHIO , HAYASHI TETSUYA , TANAKA HIDEAKI
IPC分类号： H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is capable of lowering the rise voltage without lowering the reverse withstand voltage, and to provide a manufacturing method thereof. SOLUTION: As semiconductor regions in contact with a first principal surface of a semiconductor base 100 composed by forming an N- silicon carbide epitaxial layer 2 on, for example, an N+ silicon carbide substrate 1 connected to a cathode electrode 6, both of, for example, an N+ polycrystalline silicon layer 4 of a conductivity type same as the conductivity type of the semiconductor base 100 and, for example, a P+ polycrystalline silicon layer 3 of a conductivity type different from the conductivity type of the semiconductor base 100 are provided. Both of the N+ polycrystalline silicon layer 4 and the P+ polycrystalline silicon layer 3 are hetero-joined to the semiconductor base 100, and are ohmically connected to an anode electrode 5. Moreover, the N+ polycrystalline silicon layer 4 of the conductivity type same as the conductivity type of the semiconductor base 100 is formed so as to be in contact with the first principal surface of the semiconductor base 100, and the P+ polycrystalline silicon layer 3 of the conductivity type different from the conductivity type of the semiconductor base 100 is formed in trenches dug in the first principal surface of the semiconductor base 100. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够降低上升电压而不降低反向耐受电压的半导体器件，并提供其制造方法。解决方案：通过在例如连接到阴极6的N +碳化硅衬底1上形成N-碳化硅外延层2而构成的与半导体基底100的第一主表面接触的半导体区域两者例如，与半导体基底100的导电类型相同的导电类型的N +多晶硅层4和例如不同于半导体基底100的导电类型的导电类型的P +多晶硅层3 被提供。 N +多晶硅层4和P +多晶硅层3都与半导体基底100异相接合，并且与阳极电极5欧姆连接。此外，导电类型的N +多晶硅层4与半导体基底100的导电类型形成为与半导体基底100的第一主表面接触，并且形成不同于半导体基底100的导电类型的导电类型的P +多晶硅层3 在半导体基底100的第一主表面上挖出沟槽。版权所有（C）2008，JPO＆INPIT

36. 发明专利

JP2007281270A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007281270A
公开(公告)日：2007-10-25
申请号：JP2006107129
申请日：2006-04-10
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： SHIMOIDA YOSHIO , HAYASHI TETSUYA , TANAKA HIDEAKI , YAMAGAMI SHIGEHARU , HOSHI MASAKATSU
IPC分类号： H01L29/12 , H01L21/28 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device having a low on-resistance and being capable of improving reverse characteristics and the semiconductor device.
SOLUTION: The semiconductor device has an n
+ -type hetero semiconductor region 3 arranged adjacently to a gate electrode 16, while being brought into contact with a gate insulating film 5 as a hetero semiconductor region hetero-joined with an n-type SiC drain region 2 formed on an SiC-board region 1, and connected to a source electrode 14 and a p
+ -type hetero semiconductor region 9 arranged on the SiC drain region 2. The n
+ -type hetero semiconductor region 3 is formed by patterning, using a cap insulating film 6 formed on the upper section of the gate electrode 16 and the upper section of the gate insulating film 5 in the vicinity of the gate electrode 16 as a mask. Then, the p
+ -type hetero semiconductor region 9 is formed by introducing p-type impurities to the hetero semiconductor region formed on the SiC drain region 2 exposed by an etching. The forming process of the p
+ -type hetero semiconductor region 9 is formed after forming at least the gate insulating film 5.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有低导通电阻并且能够改善反向特性的半导体器件的制造方法和半导体器件。解决方案：半导体器件具有与栅电极16相邻设置的n 型异质半导体区域3，同时与作为异质半导体区域杂质的栅极绝缘膜5接触与形成在SiC板区域1上的n型SiC漏极区域2连接，并且连接到布置在SiC漏极区域2上的源电极14和源极电极14和p + SP +型异质半导体区域9 通过使用形成在栅极电极16的上部的盖绝缘膜6和栅极绝缘膜5的上部的图案化来形成n 型异质半导体区域3 栅电极16的附近作为掩模。然后，通过将p型杂质引入形成在通过蚀刻暴露的SiC漏极区域2上的异质半导体区域而形成p + 型异质半导体区域9。至少在形成栅极绝缘膜5之后形成p + / SP>型异质半导体区域9的形成工艺。（C）2008，JPO＆INPIT

37. 发明专利

JP2007234938A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2007234938A
公开(公告)日：2007-09-13
申请号：JP2006056033
申请日：2006-03-02
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： TANAKA HIDEAKI , HOSHI MASAKATSU , HAYASHI TETSUYA , SHIMOIDA YOSHIO
IPC分类号： H01L29/78 , H01L21/337 , H01L29/12 , H01L29/80 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device capable of applying more current per unit cell, i.e. capable of further reducing ON-resistance.
SOLUTION: The silicon carbide semiconductor device has a drain region 3 consisting of an n-type silicon carbide semiconductor; a first base region 4 contacting the drain region 3 and consisting of a p-type silicon carbide semiconductor; a source region 5 contacting the first base region 4 and consisting of an n-type silicon carbide semiconductor; a second base region 6 contacting the source region 5 and consisting of a p-type silicon carbide semiconductor opposite to the first base region 4 via a predetermined region of the drain region 3; and a gate electrode 9 contacting the surface of the first base region sandwiched by at least the source region 5 and the drain region 3 via a gate insulating film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够对每单元电池施加更多电流的碳化硅半导体器件，即能够进一步降低导通电阻。解决方案：碳化硅半导体器件具有由n型碳化硅半导体构成的漏极区域3; 与漏区3接触并由p型碳化硅半导体构成的第一基区4; 与第一基极区域4接触并由n型碳化硅半导体构成的源极区域5; 与源极区域5接触的第二基极区域6，经由漏极区域3的预定区域与第一基极区域4相对的p型碳化硅半导体构成; 以及栅电极9，其经由栅极绝缘膜与至少被源极区域5和漏极区域3夹着的第一基极区域的表面接触。版权所有（C）2007，JPO＆INPIT

38. 发明专利

JP2007088383A Semiconductor device and method for manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007088383A
公开(公告)日：2007-04-05
申请号：JP2005278448
申请日：2005-09-26
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： SHIMOIDA YOSHIO , HOSHI MASAKATSU , HAYASHI TETSUYA , TANAKA HIDEAKI , YAMAGAMI SHIGEHARU , MIHARA TERUYOSHI
IPC分类号： H01L21/76 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To simplify a process for forming an isolation region and enlarge an element effective area.
SOLUTION: N-type SiC regions 1a, 1b, 1c are formed on the first principal surface side of a P+ type polysilicon substrate region, functional devices such as switching device and circuit are formed on the N-type SiC regions 1a, 1b. 1c, a backside electrode 3 is formed on the second principal surface side of a P+ type polysilicon substrate region 2, a groove reaching the P+ polysilicon substrate region 2 from the first principal surface side of the N-type SiC regions 1a, 1b, 1c, the P+ type doped polysilicon is filled inside the groove to form isolation regions 4a, 4b, wires are twisted with an external electrode so as to allow the backside electrode 3 and isolation regions 4a, 4b to be equipotential and are bonded to an earth potential.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了简化形成隔离区域的过程并扩大元件有效面积。解决方案：在P +型多晶硅衬底区域的第一主表面侧上形成N型SiC区域1a，1b，1c，在N型SiC区域1a上形成诸如开关器件和电路的功能器件， 1B。如图1c所示，在P +型多晶硅基板区域2的第二主面侧形成背面电极3，从N型SiC区域1a，1b，1c的第一主面侧到达P +多晶硅基板区域2的槽，P +型掺杂多晶硅填充在沟槽内形成隔离区域4a，4b，电线用外部电极扭曲，以使背面电极3和隔离区域4a，4b成为等电位并且接合到地电势。版权所有（C）2007，JPO＆INPIT

39. 发明专利

JP2007027491A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007027491A
公开(公告)日：2007-02-01
申请号：JP2005208798
申请日：2005-07-19
申请人： Nissan Motor Co Ltd , 日産自動車株式会社
发明人： YAMAGAMI SHIGEHARU , HOSHI MASAKATSU , HAYASHI TETSUYA , TANAKA HIDEAKI , SHIMOIDA YOSHIO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To form the widths of a polycrystalline silicon layer with introduced impurities and a hetero-semiconductor region in sufficiently narrow widths with an excellent controllability.
SOLUTION: A hard mask 7 is deposited on a p-type polycrystalline silicon layer 5 and a shallow n-type polycrystalline silicon layer 6a, and the hard mask 7 is etched selectively. The ions of n-type impurities are implanted into the p-type polycrystalline silicon layer 5 while using the hard masks 7 as masks, and n-type polycrystalline silicon layers 6 are formed. Films as a material for side walls 8 are deposited in an isotropic manner, and the side walls 8 are formed on the side faces of the hard masks 7 by an anisotropic etching using a reactive ion etching method. The n-type polycrystalline silicon layers 6 are etched while using the hard masks 7 and the side walls 8 as the masks.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了形成具有引入的杂质的多晶硅层和具有足够窄的宽度的异质半导体区域的宽度，具有优异的可控性。解决方案：在p型多晶硅层5和浅n型多晶硅层6a上沉积硬掩模7，并且选择性地蚀刻硬掩模7。使用硬掩模7作为掩模，将n型杂质的离子注入到p型多晶硅层5中，形成n型多晶硅层6。以各向同性方式沉积作为侧壁8的材料的膜，并且通过使用反应离子蚀刻方法的各向异性蚀刻，在硬掩模7的侧面上形成侧壁8。在使用硬掩模7和侧壁8作为掩模的同时蚀刻n型多晶硅层6。版权所有（C）2007，JPO＆INPIT

40. 发明专利

JP2007019095A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007019095A
公开(公告)日：2007-01-25
申请号：JP2005196533
申请日：2005-07-05
申请人： Nissan Motor Co Ltd , Rohm Co Ltd , ローム株式会社 , 日産自動車株式会社
发明人： SHIMOIDA YOSHIO , TANAKA HIDEAKI , HAYASHI TETSUYA , HOSHI MASAKATSU , YAMAGAMI SHIGEHARU , KAWAMOTO NORIAKI , KITO TAKAYUKI , MIURA MINEO , NAKAMURA TAKASHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device having a low on-resistance, a small reverse leakage current, and a high breakdown strength. SOLUTION: The manufacturing method for the semiconductor device manufacturing the semiconductor device having: a hetero semiconductor region 3 being brought into contact with one main surface of an N - SiC drain region 2 on an N + SiC substrate region 1 and having a band gap different from the drain region 2; a gate electrode 7 brought into contact with a part of a junction section between the hetero semiconductor region 3 and the drain region 2 through a gate insulating film 6; a source electrode 8 connected to the hetero semiconductor region 3; and a drain electrode 9 ohmic-connected to the substrate region 1. In the manufacturing method for the semiconductor device, the gate insulating film 6 is nitriding-treated (such as an annealing treatment at a high temperature under an N 2 O-containing atmosphere) after the formation of the gate insulating film 6. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有低导通电阻，小的反向漏电流和高击穿强度的半导体器件的制造方法。解决方案：制造半导体器件的半导体器件的制造方法具有：异质半导体区域3与N - SiC漏极区域2的一个主表面接触， SP> + SiC衬底区域1并且具有与漏极区域2不同的带隙; 栅电极7通过栅极绝缘膜6与异质半导体区域3和漏极区域2之间的接合部分的一部分接触; 连接到异质半导体区域3的源电极8; 以及与基板区域1欧姆连接的漏电极9.在半导体装置的制造方法中，将栅极绝缘膜6进行氮化处理（例如，在N 2℃的高温下进行退火处理， / SB>含O气氛）。形成栅绝缘膜6后，（C）2007，JPO＆INPIT

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