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31. 发明申请

US20080320064A1 Method and apparatus for controlling reading level of memory cell 有权
标题翻译：用于控制存储单元的读取电平的方法和装置
公开(公告)号：US20080320064A1
公开(公告)日：2008-12-25
申请号：US12003545
申请日：2007-12-28
申请人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Seung-Hwan Song , Dong Ku Kang
IPC分类号： G06F1/16
CPC分类号： G11C16/28 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/0411
摘要： A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.
摘要翻译：提供了一种用于控制存储单元的读取电平的方法和装置。控制存储器单元的读取电平的方法可以包括：接收基于给定电压电平和参考电平计算出的度量值; 通过对应于来自接收到的度量值中的接收信号的电平的度量值相加来产生每个参考电平的相加值; 从所述参考电平中选择具有所生成的总和值的最大值的参考电平; 以及基于所选择的参考电平来控制所述存储器单元的读取电平。

32. 发明申请

US20080288853A1 Apparatus and method of puncturing of error control codes 审中-公开
标题翻译：打孔错误控制代码的设备和方法
公开(公告)号：US20080288853A1
公开(公告)日：2008-11-20
申请号：US11889410
申请日：2007-08-13
申请人： Jun Jin Kong , Jong Han Kim , Hong Rak Son , Young Hwan Lee , Sung Chung Park , Seung-Hwan Song
发明人： Jun Jin Kong , Jong Han Kim , Hong Rak Son , Young Hwan Lee , Sung Chung Park , Seung-Hwan Song
IPC分类号： H03M13/03
CPC分类号： H03M13/6362
摘要： A code puncturing apparatus and method is provided. The apparatus includes: a codeword selection unit selecting continuous n−1-number of mother codewords from mother codewords generated from k-bit effective information, where k denotes a natural number, and one redundancy bit; and a puncturing unit selecting k-number of redundancy bits from redundancy bits included in the n−1-number of mother codewords, deleting remaining redundancy bits, and rearranging the n−1-number of mother codewords into an n·k bit-target codeword. Accordingly, a code rate of an Error Control Code (ECC) can be raised.
摘要翻译：提供了一种代码穿刺装置和方法。该装置包括：码字选择单元，从k比特有效信息生成的母码中选择连续n-1个母码字，其中k表示自然数，一个冗余比特; 以及删截单元，从包含在n-1个母码字中的冗余比特中选择k个冗余比特，删除剩余的冗余比特，并将n-1个母码字重排为nk比特目标码字。因此，可以提高错误控制码（ECC）的码率。

33. 发明授权

US08274840B2 Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法
公开(公告)号：US08274840B2
公开(公告)日：2012-09-25
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

34. 发明申请

US20100091578A1 Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同
公开(公告)号：US20100091578A1
公开(公告)日：2010-04-15
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

35. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

36. 发明授权

US08230157B2 Memory device and method of multi-bit programming 失效
标题翻译：多位编程的存储器件和方法
公开(公告)号：US08230157B2
公开(公告)日：2012-07-24
申请号：US12155647
申请日：2008-06-06
申请人： Jaehong Kim , Kyoung Lae Cho , Jun Jin Kong , Heeseok Eun , Seung-Hwan Song
发明人： Jaehong Kim , Kyoung Lae Cho , Jun Jin Kong , Heeseok Eun , Seung-Hwan Song
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/00 , G06F11/10 , H03M13/00 , G11C29/00
CPC分类号： G11C11/5628 , G11C11/5671 , G11C29/00
摘要： Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.
摘要翻译：提供了存储器件和多位编程方法。存储器件可以包括多个存储器单元; 数据分离器，将数据分离成多个组; 选择器，其使所述多个组中的每一个旋转，并将所述组中的每一个发送到所述多个存储器单元中的至少一个。多个存储器单元可以包括可以使用页面编程操作的不同顺序对多个多位单元阵列中的发送组进行编程的页缓冲器。通过此，可能会生成均匀可靠的数据页。

37. 发明授权

US08085599B2 Memory device and method for estimating characteristics of multi-bit programming 有权
标题翻译：用于估计多位编程特性的存储器件和方法
公开(公告)号：US08085599B2
公开(公告)日：2011-12-27
申请号：US12801505
申请日：2010-06-11
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

38. 发明申请

US20100254195A1 Memory device and method for estimating characteristics of multi-bit programming 有权
标题翻译：用于估计多位编程特性的存储器件和方法
公开(公告)号：US20100254195A1
公开(公告)日：2010-10-07
申请号：US12801505
申请日：2010-06-11
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae Hong Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

39. 发明申请

US20090175076A1 Memory device and method for estimating characteristics of multi-bit cell 有权
标题翻译：用于估计多位单元特性的存储器件和方法
公开(公告)号：US20090175076A1
公开(公告)日：2009-07-09
申请号：US12213657
申请日：2008-06-23
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
IPC分类号： G11C16/00 , G11C7/00
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

40. 发明授权

US08305818B2 Memory device and method for estimating characteristics of multi-bit programming 有权
标题翻译：用于估计多位编程特性的存储器件和方法
公开(公告)号：US08305818B2
公开(公告)日：2012-11-06
申请号：US13303353
申请日：2011-11-23
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

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