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31. 发明授权

US07664905B2 Page stream sorter for poor locality access patterns 有权
标题翻译：页面流排序器用于不良的局部访问模式
公开(公告)号：US07664905B2
公开(公告)日：2010-02-16
申请号：US11592540
申请日：2006-11-03
申请人： David A. Jarosh , Sonny S. Yeoh , Colyn S. Case , John H. Edmondson
发明人： David A. Jarosh , Sonny S. Yeoh , Colyn S. Case , John H. Edmondson
IPC分类号： G06F13/14
CPC分类号： G06F13/1626
摘要： In some applications, such as video motion compression processing for example, a request pattern or “stream” of requests for accesses to memory (e.g., DRAM) may have, over a large number of requests, a relatively small number of requests to the same page. Due to the small number of requests to the same page, conventionally sorting to aggregate page hits may not be very effective. Reordering the stream can be used to “bury” or “hide” much of the necessary precharge/activate time, which can have a highly positive impact on overall throughput. For example, separating accesses to different rows of the same bank by at least a predetermined number of clocks can effectively hide the overhead involved in precharging/activating the rows.
摘要翻译：在一些应用中，例如视频运动压缩处理，例如，对存储器（例如，DRAM）访问的请求的请求模式或“流”可以在大量请求中具有相对较少数量的请求页。由于对同一页面的请求数量不多，常规排序以汇总页面命中可能不是很有效。重新排序流可以用于“埋葬”或“隐藏”大量必要的预充/激活时间，这对整体吞吐量可能产生很大的积极影响。例如，将对相同存储体的不同行的访问分离至少预定数量的时钟可以有效地隐藏预充电/激活行所涉及的开销。

32. 发明授权

US06272624B1 Method and apparatus for predicting multiple conditional branches 有权
标题翻译：用于预测多个条件分支的方法和装置
公开(公告)号：US06272624B1
公开(公告)日：2001-08-07
申请号：US09285529
申请日：1999-04-02
申请人： Glenn P. Giacalone , John H. Edmondson
发明人： Glenn P. Giacalone , John H. Edmondson
IPC分类号： G06F9305
CPC分类号： G06F9/3848
摘要： The outcome of a plurality of branch instructions in a computer program is predicted by fetching a plurality or group of instructions in a given slot, along with a corresponding prediction. A group global history (gghist) is maintained to indicate of recent program control flow. In addition, a predictor table comprising a plurality of predictions, preferably saturating counters. A particular counter is updated when a branch is encountered. The particular counter is associated with a branch instruction by hashing the fetched instruction group's program counter (PC) with the gghist. To predict multiple branch instruction outcomes, the gghist is hashed with the PC to form an index which is used to access naturally aligned but randomly ordered predictions in the predictor table, which are then reordered based on value of the lower gghits bits. Preferably, instructions are fetched in blocks of eight instructions. The gghist is maintained by shifting in a 1 if a branch in the corresponding group is taken, or a 0 if no branch in the corresponding group is taken. The hashing function is preferably an XOR operation. Preferably, a predictor table counter is incremented when a corresponding branch is taken, but not beyond a maximum value, and is decremented when the corresponding branch is not taken, but not below zero. Preferably, the most significant bit of a counter is used to determine a prediction.
摘要翻译：计算机程序中的多个分支指令的结果通过在给定时隙中取出多个或一组指令以及相应的预测来预测。维持组织全球历史（gghist）以指示最近的程序控制流程。另外，预测器表包括多个预测，优选饱和计数器。遇到分支时，会更新一个特定的计数器。特定计数器与分支指令相关联，通过用gghist散列获取的指令组的程序计数器（PC）。为了预测多个分支指令结果，gghist与PC进行散列以形成一个索引，用于访问预测器表中的自然对齐但随机排序的预测，然后基于较低g比特位的值重新排序。优选地，指令以八个指令的块来获取。如果相应组中的分支被采用，则通过在1中移位来维持高斯特，或者如果不对应组中的分支，则为0。散列函数优选为异或运算。优选地，当相应的分支被采取但不超过最大值时，预测器表计数器递增，并且当相应的分支未被采用但不低于零时递减。优选地，计数器的最高有效位用于确定预测。

33. 发明授权

US08949541B2 Techniques for evicting dirty data from a cache using a notification sorter and count thresholds 有权
标题翻译：使用通知排序器和计数阈值从缓存中排除脏数据的技术
公开(公告)号：US08949541B2
公开(公告)日：2015-02-03
申请号：US13296119
申请日：2011-11-14
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John H. Edmondson
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804
摘要： A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
摘要翻译：公开了一种用于清除中间高速缓存中的脏数据的方法。当脏数据存储在L2高速缓存中时，包含存储器地址和数据类的脏数据通知由级别2（L2）高速缓存发送到帧缓冲器逻辑。数据类可能包括首先驱逐，最后驱逐正常和驱逐。在一个实施例中，属于第一数据类别的数据是具有很少重用潜力的光栅操作数据。帧缓冲器逻辑使用通知排序器来组织脏数据通知，其中通知分类器中的条目存储DRAM存储体页面编号，具有驻留脏数据的高速缓存行的第一计数和具有居民驱逐器的第一高速缓存行计数与该DRAM库相关联的脏数据。当第一计数达到阈值时，帧缓冲器逻辑发送与条目相关联的脏数据。

34. 发明授权

US08700865B1 Compressed data access system and method 有权
标题翻译：压缩数据访问系统和方法
公开(公告)号：US08700865B1
公开(公告)日：2014-04-15
申请号：US11592819
申请日：2006-11-02
申请人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
发明人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F12/1009 , G06F2212/401
摘要： A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.
摘要翻译：描述了共享资源管理系统和方法。在一个实施例中，共享资源管理系统包括多个引擎，共享资源和共享资源管理单元。在一个示例性实现中，共享资源是存储器，共享资源管理单元是存储器管理单元（MMU）。多个发动机执行处理。共享资源支持处理。例如，存储器存储引擎的信息和指令。共享资源管理单元管理存储器操作并处理与压缩数据相关联的访问请求。

35. 发明授权

US08656093B1 Supporting late DRAM bank hits 有权
标题翻译：支持晚期DRAM银行点击
公开(公告)号：US08656093B1
公开(公告)日：2014-02-18
申请号：US12326063
申请日：2008-12-01
申请人： John H. Edmondson , Shane Keil
发明人： John H. Edmondson , Shane Keil
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/28
摘要： One embodiment of the invention sets forth a mechanism to transmit commands received from an L2 cache to a bank page within the DRAM. An arbiter unit determines which commands from a command sorter to transmit to a command queue. An activate command associated with the bank page related to the commands is also transmitted to an activate queue. The last command in the command queue is marked as “last.” An interlock counter stores a count of “last” commands in the read/write command queue. A DRAM controller transmits activate and commands from the activate queue and the command queue to the DRAM. Each time a command marked as “last” is encountered, the DRAM controller decrements the interlock counter. If the count in the interlock counter is zero, then the command marked as “last” is marked as “auto-precharge.” The “auto-precharge” command, when processed, causes the bank page to be closed.
摘要翻译：本发明的一个实施例提出了一种将从L2高速缓存接收的命令发送到DRAM内的存储体页面的机制。仲裁器单元确定哪些命令从命令分拣机发送到命令队列。与该命令相关联的存储体页面的激活命令也被发送到激活队列。命令队列中的最后一个命令被标记为“last”。互锁计数器在读/写命令队列中存储“最后”命令的计数。 DRAM控制器将激活和命令从激活队列和命令队列传送到DRAM。每当遇到标记为“last”的命令时，DRAM控制器递减互锁计数器。如果互锁计数器中的计数为零，则标记为“last”的命令被标记为“自动预充电”。 “自动预充电”命令在处理时导致银行页关闭。

36. 发明申请

US20130311686A1 MECHANISM FOR TRACKING AGE OF COMMON RESOURCE REQUESTS WITHIN A RESOURCE MANAGEMENT SUBSYSTEM 有权
标题翻译：跟踪资源管理子系统中共同资源年龄的机制
公开(公告)号：US20130311686A1
公开(公告)日：2013-11-21
申请号：US13476825
申请日：2012-05-21
申请人： Michael FETTERMAN , Shirish Gadre , John H. Edmondson , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Rajeshwaran Selvanesan , Charles McCarver , Kevin Mitchell , Steven James Heinrich
发明人： Michael FETTERMAN , Shirish Gadre , John H. Edmondson , Omkar Paranjape , Anjana Rajendran , Eric Lyell Hill , Rajeshwaran Selvanesan , Charles McCarver , Kevin Mitchell , Steven James Heinrich
IPC分类号： G06F5/00
CPC分类号： H04L49/254 , G06F9/46
摘要： One embodiment of the present disclosure sets forth an effective way to maintain fairness and order in the scheduling of common resource access requests related to replay operations. Specifically, a streaming multiprocessor (SM) includes a total order queue (TOQ) configured to schedule the access requests over one or more execution cycles. Access requests are allowed to make forward progress when needed common resources have been allocated to the request. Where multiple access requests require the same common resource, priority is given to the older access request. Access requests may be placed in a sleep state pending availability of certain common resources. Deadlock may be avoided by allowing an older access request to steal resources from a younger resource request. One advantage of the disclosed technique is that older common resource access requests are not repeatedly blocked from making forward progress by newer access requests.
摘要翻译：本公开的一个实施例阐述了在与重放操作相关的公共资源访问请求的调度中维持公平性和顺序的有效方式。具体地说，流式多处理器（SM）包括配置成通过一个或多个执行周期调度访问请求的总顺序队列（TOQ）。访问请求被允许在需要时将共同资源分配给该请求来进行进展。在多个访问请求需要相同的公共资源的情况下，优先级被赋予较旧的访问请求。访问请求可能处于睡眠状态，等待某些公共资源的可用性。可以通过允许较旧的访问请求从较年轻的资源请求中窃取资源来避免死锁。所公开的技术的一个优点是较旧的公共资源访问请求不被重复阻止以通过较新的访问请求提前进展。

37. 发明授权

US08307165B1 Sorting requests to the DRAM for high page locality 有权
标题翻译：将请求排序到DRAM以获得高页面位置
公开(公告)号：US08307165B1
公开(公告)日：2012-11-06
申请号：US12501351
申请日：2009-07-10
申请人： Shane Keil , John H. Edmondson , Sean J. Treichler
发明人： Shane Keil , John H. Edmondson , Sean J. Treichler
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1631
摘要： One embodiment of the invention sets forth a mechanism for increasing the number of read commands or write commands transmitted to an activated bank page in the DRAM. Read requests and dirty notifications are organized in a read request sorter or a dirty notification sorter, respectively, and each sorter includes multiple sets with entries that may be associated with different bank pages in the DRAM. Read requests and dirty notifications are stored in read request lists and dirty notification lists, where each list is associated with a specific bank page. When a bank page is activated to process read requests, read commands associated with read requests stored in a particular read request list are transmitted to the bank page. When a bank page is activated to process dirty notifications, write commands associated with dirty notifications stored in a particular dirty notification list are transmitted to the bank page.
摘要翻译：本发明的一个实施例提出了一种用于增加发送到DRAM中的激活的存储体页面的读取命令或写入命令的数量的机制。读取请求和脏通知分别组织在读请求分类器或脏通知分类器中，并且每个分类器包括具有可与DRAM中的不同存储区页相关联的条目的多个集合。读取请求和脏通知存储在读取请求列表和脏通知列表中，每个列表与特定的银行页面相关联。当激活银行页面以处理读取请求时，读取与存储在特定读取请求列表中的读取请求相关联的命令被发送到银行页面。激活银行页面以处理脏通知时，与存储在特定脏通知列表中的脏通知相关联的写入命令被发送到银行页面。

38. 发明授权

US08234478B1 Using a data cache array as a DRAM load/store buffer 有权
标题翻译：使用数据高速缓存阵列作为DRAM加载/存储缓冲区
公开(公告)号：US08234478B1
公开(公告)日：2012-07-31
申请号：US12256400
申请日：2008-10-22
申请人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
发明人： James Roberts , David B. Glasco , Patrick R. Marchand , Peter B. Holmqvist , George R. Lynch , John H. Edmondson
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895
摘要： One embodiment of the invention sets forth a mechanism for using the L2 cache as a buffer for data associated with read/write commands that are processed by the frame buffer logic. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves necessary cache lines for the read/write operations and transmits read commands to the frame buffer logic for processing. A data slice scheduler transmits a dirty data notification to the frame buffer logic when data associated with a write command is stored in an SRAM bank. The data slice scheduler schedules accesses to the SRAM banks and gives priority to accesses requested by the frame buffer logic to store or retrieve data associated with read/write commands. This feature allows cache lines reserved for read/write commands that are processed by the frame buffer logic to be made available at the earliest clock cycle.
摘要翻译：本发明的一个实施例提出了一种使用L2高速缓存作为与由帧缓冲器逻辑处理的读/写命令相关联的数据的缓冲器的机制。标签查找单元跟踪L2高速缓存中每个高速缓存行的可用性，为读/写操作预留必要的高速缓存行，并将读命令发送到帧缓冲器逻辑进行处理。当与写命令相关联的数据被存储在SRAM存储体中时，数据片调度器将脏数据通知发送到帧缓冲器逻辑。数据片调度器调度对SRAM组的访问，并且优先级由帧缓冲器逻辑请求的访问来存储或检索与读/写命令相关联的数据。该功能允许由帧缓冲器逻辑处理的读/写命令保留的高速缓存行在最早的时钟周期内可用。

39. 发明授权

US5987544A System interface protocol with optional module cache 失效
标题翻译：具有可选模块缓存的系统接口协议
公开(公告)号：US5987544A
公开(公告)日：1999-11-16
申请号：US525114
申请日：1995-09-08
申请人： Peter J. Bannon , Anil K. Jain , John H. Edmondson , Ruben William Sixtus Castelino
发明人： Peter J. Bannon , Anil K. Jain , John H. Edmondson , Ruben William Sixtus Castelino
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0831
摘要： A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.
摘要翻译：计算机系统包括耦合到系统总线的多个处理器模块，每个所述处理器模块包括与系统总线接口的处理器。处理器模块具有备份高速缓存和标签存储。索引总线耦合在处理器和备份高速缓存和备份高速缓存标签存储之间，所述总线仅将存储器地址的索引部分携带到所述备份高速缓存和所述标签存储。重复标签存储器与重复标签存储器耦合到接口，包括用于存储重复标签地址和重复标签有效，共享和脏位的装置。重复标签存储和单独的索引总线通过最小化处理器的外部中断来检查高速缓存状态，从处理器提供更高的性能，并且还允许其他处理器在处理器处理其他事务时访问处理器的重复标签。

40. 发明授权

US5615167A Method for increasing system bandwidth through an on-chip address lock register 失效
标题翻译：通过片上地址锁定寄存器增加系统带宽的方法
公开(公告)号：US5615167A
公开(公告)日：1997-03-25
申请号：US525106
申请日：1995-09-08
申请人： Anil K. Jain , John H. Edmondson , Peter J. Bannon
发明人： Anil K. Jain , John H. Edmondson , Peter J. Bannon
IPC分类号： G06F9/46 , G11C13/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.
摘要翻译：一种包括一个或多个处理器模块的计算机系统。每个处理器模块包括中央处理单元，该中央处理单元包括设置在专用于存储信号量地址锁定值和信号量锁定标志值的中央处理单元中的存储元件，用于存储由中央处理单元使用的数据和指令值的高速缓冲存储器系统，用于通过系统总线与其他处理器模块通信的系统总线接口，被实现为用于存储数据和指令的处理器模块可用的公共系统资源的存储器系统，被实现为可用于多个处理器的公共系统资源的IO系统每个模块用于与数据输入设备和数据输出设备通信，以及将处理器模块连接到存储器系统和IO系统的系统总线。

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