专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20070271494A1 Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices 有权
标题翻译：闪存设备中多扇区页面的错误校正编码
公开(公告)号：US20070271494A1
公开(公告)日：2007-11-22
申请号：US11383844
申请日：2006-05-17
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G11C29/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F2212/7202 , G06F2212/7207
摘要： A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.
摘要翻译：公开了一种包括闪速存储器件和控制器并且具有改进的效率纠错编码（ECC）的闪速存储器系统。闪存设备中的每个页面都有能力存储多个扇区的数据。然而，由于可靠性原因，禁止部分页面编程（即，随后稍后写入以填充页面）。设计闪存器件内的暂存器块，并存储用户数据和控制数据。通过对与用户对应的整个数据块和页面中的控制数据对ECC或奇偶校验位进行编码来提高ECC效率。检索特定的数据部分需要读取和解码整个页面。特别是对于诸如Reed-Solomon和BCH码之类的代码，包括多个扇区数据的较大的数据块改善了纠错能力，从而使每一页中的冗余存储单元更少或改进了纠错。

32. 发明授权

US07215580B2 Non-volatile memory control 有权
标题翻译：非易失性存储器控制
公开(公告)号：US07215580B2
公开(公告)日：2007-05-08
申请号：US10867800
申请日：2004-06-14
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G11C7/10
CPC分类号： G06F13/1615 , G06F3/0625 , G06F3/0659 , G06F3/0688 , G06F13/4239 , G11C7/1039 , Y02D10/154
摘要： According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.
摘要翻译：根据本发明的实施例，提供了一种用于具有非易失性存储器的存储器系统中的方法和装置，以及用于从一个存储的多个可用阵列限制非易失性存储器阵列的数量的控制器时间，其中所述方法包括实现用于将数据传送到非易失性存储器阵列和从所述非易失性存储器阵列传送数据并限制一次操作的有效阵列的数量的流水线序列，所述布置使得所述控制器等待所述阵列中的所述至少一个阵列在开始转移到另一个数组之前完成。

33. 发明授权

US07185208B2 Data processing 有权
标题翻译：数据处理
公开(公告)号：US07185208B2
公开(公告)日：2007-02-27
申请号：US10260136
申请日：2002-09-27
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G06F11/30 , H04L9/00 , H04N7/167
CPC分类号： G06F21/79 , G06F12/1408 , G06F21/6209 , G06F2221/2107
摘要： In one embodiment of the present invention, there is disclosed a reversible method of processing data comprising the data being encrypted before being written to a non-volatile memory wherein the data cannot be accessed without decryption in the case of a direct physical access to the non-volatile memory.
摘要翻译：在本发明的一个实施例中，公开了一种处理数据的可逆方法，该数据包括在被写入非易失性存储器之前被加密的数据，其中在对非非易失性存储器进行直接物理访问的情况下，无法解密数据，非易失存储器

34. 发明授权

US06725321B1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US06725321B1
公开(公告)日：2004-04-20
申请号：US09786418
申请日：2001-03-01
申请人： Alan Welsh Sinclair , Natalia Victorovna Ouspenskaia , Richard Michael Taylor , Sergey Anatolievich Gorobets
发明人： Alan Welsh Sinclair , Natalia Victorovna Ouspenskaia , Richard Michael Taylor , Sergey Anatolievich Gorobets
IPC分类号： G06F1200
CPC分类号： G06F12/0246 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F2212/7202
摘要： A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.
摘要翻译：一种具有固态存储器（6）的存储器系统（10），该固态存储器（6）包括布置在可擦除块中的非易失性单独可寻址存储器扇区（1），以及用于写入从扇区读取并将块分类为 “擦除”和“不擦除”块。控制器执行逻辑到物理地址转换，并且包括用于指向要从主机处理器写入数据的物理扇区地址的写指针（WP）。具有相应物理地址的逻辑地址的扇区分配表（SAT）被存储在存储器中，并且控制器比扇区被写入的频率比主处理器的数据更频繁地更新SAT。存储器可以在单个芯片中，或者在多个芯片中。还要求用于在各个扇区（1）中排列数据的新颖系统。

35. 发明授权

US09032134B2 Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a host if a logical sector is indicated as being erased 有权
标题翻译：如果逻辑扇区被指示为被擦除，则操作包括从扇区分配表向主机输出数据模式的存储器系统的方法
公开(公告)号：US09032134B2
公开(公告)日：2015-05-12
申请号：US13417715
申请日：2012-03-12
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0679
摘要： A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory, determining whether the logical sector of the memory is indicated as being erased in a sector allocation table, if the logical sector of the memory is indicated as being erased, outputting a data pattern from the sector allocation table to the host, and if the logical sector of the memory is not indicated as being erased, reading a physical sector of the memory and outputting data from the physical sector of the memory to the host.
摘要翻译：操作存储器系统的方法包括从主机接收读取命令，其中读取命令与存储器的逻辑扇区相关联，确定存储器的逻辑扇区是否被指示为在扇区分配表中被擦除，如果存储器的逻辑扇区被指示为被擦除，从扇区分配表向主机输出数据模式，并且如果存储器的逻辑扇区未被指示为被擦除，则读取存储器的物理扇区并输出数据从内存的物理扇区到主机。

36. 发明授权

US08700840B2 Nonvolatile memory with write cache having flush/eviction methods 有权
标题翻译：具有写入缓存的非易失性存储器具有刷新/驱逐方法
公开(公告)号：US08700840B2
公开(公告)日：2014-04-15
申请号：US12348895
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/08 , G11C11/34
CPC分类号： G06F12/0866 , G06F12/0246 , G06F12/0804 , G06F2212/7203 , G06F2212/7204 , G11C11/5628 , G11C2211/5641 , Y02D10/13
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。

37. 发明申请

US20130326128A1 Methods and Apparatus for Passing Information to a Host System to Suggest Logical Locations to Allocate to a File 有权
标题翻译：将信息传递给主机系统以建议分配到文件的逻辑位置的方法和装置
公开(公告)号：US20130326128A1
公开(公告)日：2013-12-05
申请号：US13961388
申请日：2013-08-07
申请人： Sergey Anatolievich Gorobets
发明人： Sergey Anatolievich Gorobets
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0616 , G06F3/0631 , G06F3/0643 , G06F3/0688 , G06F2212/7202 , Y02D10/13
摘要： Methods and apparatus for passing information to a host system to suggest logical locations to allocate to a file are disclosed. Generally, when a host system determines a need to allocate a logical location to a file, the host system sends a non-data command to a memory system. In response, the memory system sends information to the host system that includes one or more logical locations to allocate to the file. By suggesting one or more logical locations to allocate to a file, the memory system may reduce a number of data consolidation or garbage collection operations that will need to be performed in the future, thereby improving performance of the memory system.
摘要翻译：公开了用于将信息传递到主机系统以建议分配给文件的逻辑位置的方法和装置。通常，当主机系统确定需要向文件分配逻辑位置时，主机系统向存储器系统发送非数据命令。作为响应，存储器系统向包括一个或多个逻辑位置的主机系统发送信息以分配给该文件。通过建议一个或多个逻辑位置来分配给文件，存储器系统可以减少将来需要执行的数量合并或垃圾收集操作的数量，从而提高存储器系统的性能。

38. 发明授权

US08543757B2 Techniques of maintaining logical to physical mapping information in non-volatile memory systems 有权
标题翻译：在非易失性存储器系统中维护逻辑到物理映射信息的技术
公开(公告)号：US08543757B2
公开(公告)日：2013-09-24
申请号：US12821423
申请日：2010-06-23
申请人： Sergey Anatolievich Gorobets , Robert George Young
发明人： Sergey Anatolievich Gorobets , Robert George Young
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205 , G06F2212/7207
摘要： A non-volatile memory system writes logical to physical conversion data to the same memory blocks as user data, and as part of the same page as a segment of user data, as data segments are received and written. When a data block is subsequently compacted and obsolete data removed, the user data from the block is written to a one block and some or all of the logical to physical conversion data from the block is written to another block dedicated for the storage of such logical to physical mapping data.
摘要翻译：非易失性存储器系统将物理转换数据逻辑写入与用户数据相同的存储器块，并且作为与用户数据段相同的页面的一部分，作为数据段被接收和写入。当随后压缩数据块并去除过时的数据时，来自块的用户数据被写入一个块，并且来自块的逻辑到物理转换数据的一些或全部被写入专用于存储这种逻辑的另一个块到物理映射数据。

39. 发明授权

US08417876B2 Use of guard bands and phased maintenance operations to avoid exceeding maximum latency requirements in non-volatile memory systems 有权
标题翻译：使用保护频段和分阶段的维护操作，以避免在非易失性存储器系统中超过最大延迟要求
公开(公告)号：US08417876B2
公开(公告)日：2013-04-09
申请号：US12821759
申请日：2010-06-23
申请人： Sergey Anatolievich Gorobets , Robert George Young , Alan David Bennett
发明人： Sergey Anatolievich Gorobets , Robert George Young , Alan David Bennett
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： Techniques are presented for performing maintenance operations, such as garbage collection, on non-volatile memory systems will still respecting the maximum latency, or time-out, requirements of a protocol. A safety guard band in the space available for storing host data, control data, or both, is provided. If, on an access of the memory, it is determined that the guard band space is exceeded, the system uses a recovery back to the base state by triggering and prioritizing clean-up operations to re-establish all safety guard bands without breaking the timing requirements. To respect these timing requirements, the operations are split into portions and done in a phased manner during allowed latency periods.
摘要翻译：提出了用于执行维护操作（例如垃圾收集）的技术，在非易失性存储器系统上仍将遵守协议的最大等待时间或超时要求。提供了可用于存储主机数据，控制数据或两者的空间中的安全保护带。如果在存储器的访问上确定超过了保护带空间，则系统通过触发并清除清除操作的优先级将恢复恢复到基本状态，以重新建立所有安全保护带而不破坏时序要求。为了遵守这些时序要求，在允许的等待时间期间，操作被分成多个部分并以分阶段的方式完成。

40. 发明授权

US08244960B2 Non-volatile memory and method with write cache partition management methods 有权
标题翻译：非易失性存储器和写入缓存分区管理方法
公开(公告)号：US08244960B2
公开(公告)日：2012-08-14
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。优选地，分配耐力计数高于平均值的块。数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式