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31. 发明申请

US20050199958A1 Method for selectively stressing MOSFETs to improve charge carrier mobility 有权
标题翻译：选择性地强迫MOSFET以改善载流子迁移率的方法
公开(公告)号：US20050199958A1
公开(公告)日：2005-09-15
申请号：US10798960
申请日：2004-03-10
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

32. 发明授权

US07482211B2 Junction leakage reduction in SiGe process by implantation 有权
标题翻译：通过植入SiGe工艺中的结漏电减少
公开(公告)号：US07482211B2
公开(公告)日：2009-01-27
申请号：US11523274
申请日：2006-09-19
申请人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
发明人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在与栅电极的边缘相邻的半导体衬底中形成应力器，并在形成步骤之后注入杂质压力源。杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

33. 发明授权

US07361572B2 STI liner modification method 有权
标题翻译： STI衬垫修改方法
公开(公告)号：US07361572B2
公开(公告)日：2008-04-22
申请号：US11059728
申请日：2005-02-17
申请人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

34. 发明授权

US07259050B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259050B2
公开(公告)日：2007-08-21
申请号：US10834474
申请日：2004-04-29
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
IPC分类号： H01L21/338
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
摘要翻译：半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

35. 发明申请

US20070010073A1 Method of forming a MOS device having a strained channel region 审中-公开
标题翻译：形成具有应变通道区域的MOS器件的方法
公开(公告)号：US20070010073A1
公开(公告)日：2007-01-11
申请号：US11175563
申请日：2005-07-06
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/76828 , H01L21/76829 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.
摘要翻译：一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶并且提供基本上所有的应变封盖层的去除。该方法还包括在超退火之前对源极/漏极区进行非晶化。应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。在去除应变封盖层后产生并保存菌株。

36. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

37. 发明申请

US20050136583A1 Advanced strained-channel technique to improve CMOS performance 审中-公开
标题翻译：先进的应变通道技术，以提高CMOS性能
公开(公告)号：US20050136583A1
公开(公告)日：2005-06-23
申请号：US10744746
申请日：2003-12-23
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823842
摘要： A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the structure and the gate electrode. The gate electrode is annealed to achieve tensile stress in the channel.
摘要翻译：一种提高CMOS器件性能的方法，包括以下步骤。提供了具有形成在其上的栅电极和在其下形成的沟道的结构。栅电极具有初始下宽度和初始上宽度。在结构和栅电极上形成具有拉伸应力的覆盖层。栅电极退火以在通道中实现拉伸应力。

38. 发明授权

US08557669B2 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US08557669B2
公开(公告)日：2013-10-15
申请号：US12176655
申请日：2008-07-21
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/42
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
摘要翻译：提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。应力诱导层可以是凹陷区域或非凹陷区域。第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

39. 发明申请

US20080160709A1 Advanced activation approach for MOS devices 有权
标题翻译： MOS器件的高级激活方法
公开(公告)号：US20080160709A1
公开(公告)日：2008-07-03
申请号：US11648371
申请日：2006-12-29
申请人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
发明人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

40. 发明申请

US20070284615A1 Ultra-shallow and highly activated source/drain extension formation using phosphorus 有权
标题翻译：使用磷的超浅和高活化的源/漏延伸形成
公开(公告)号：US20070284615A1
公开(公告)日：2007-12-13
申请号：US11521660
申请日：2006-09-15
申请人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
发明人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0847 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
摘要翻译：半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

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