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31. 发明授权

US08252639B2 Thin film transistor array panel and method for manufacturing the same 失效
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08252639B2
公开(公告)日：2012-08-28
申请号：US12951981
申请日：2010-11-22
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在所述栅极绝缘层上且与所述栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

32. 发明授权

US07998786B2 Method of manufacturing a TFT array panel 有权
标题翻译：制造TFT阵列面板的方法
公开(公告)号：US07998786B2
公开(公告)日：2011-08-16
申请号：US12369839
申请日：2009-02-12
申请人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
发明人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
IPC分类号： H01L21/00
CPC分类号： H01L29/66765 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).
摘要翻译：在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。铝层沉积在钼层上。可以在铝层上形成另一金属层。钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

33. 发明授权

US07843518B2 LCD aperture ratios 有权
标题翻译： LCD开口率
公开(公告)号：US07843518B2
公开(公告)日：2010-11-30
申请号：US11975968
申请日：2007-10-22
申请人： Sung-Hoon Yang , So-Woon Kim , Chong-Chul Chai , Chang-Oh Jeong , Eun-Guk Lee , Je-Hun Lee
发明人： Sung-Hoon Yang , So-Woon Kim , Chong-Chul Chai , Chang-Oh Jeong , Eun-Guk Lee , Je-Hun Lee
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213 , G02F1/136227 , G02F2201/40
摘要： A display substrate includes respective pluralities of gate lines, data lines, switching elements, storage lines, pixel electrodes, and an organic insulation layer. The gate lines and the data lines define a plurality of unit pixels. The storage lines are respectively formed adjacent to the respective drain electrodes of the respective switching elements of respective rows of the unit pixels. The organic insulation layer has a hole that is formed within the area of each of the unit pixels and that extends from a contact area formed at a portion of the corresponding drain electrode of the pixel to a portion corresponding to the storage line thereof. This arrangement enables the marginal area needed to prevent mismatch of the hole in the areas of the contact area and the storage line to be reduced, thereby increasing the aperture ratio of the display.
摘要翻译：显示基板包括多条栅极线，数据线，开关元件，存储线，像素电极和有机绝缘层。栅极线和数据线限定多个单位像素。存储线分别形成为与各行的单位像素的各个开关元件的各个漏电极相邻。有机绝缘层具有形成在每个单位像素的区域内的孔，并且从形成在像素的相应漏电极的一部分的接触区域延伸到对应于其存储线的部分。这种布置使得能够减小接触区域和存储线的区域中的孔的失配所需的边缘区域，从而增加显示器的开口率。

34. 发明授权

US07352004B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07352004B2
公开(公告)日：2008-04-01
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

35. 发明申请

US20060102907A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060102907A1
公开(公告)日：2006-05-18
申请号：US11228852
申请日：2005-09-16
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
摘要翻译：本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

36. 发明授权

US08207534B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08207534B2
公开(公告)日：2012-06-26
申请号：US12417280
申请日：2009-04-02
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

37. 发明申请

US20110284857A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110284857A1
公开(公告)日：2011-11-24
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

38. 发明申请

US20110065220A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110065220A1
公开(公告)日：2011-03-17
申请号：US12951981
申请日：2010-11-22
申请人： Je-Hun LEE , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun LEE , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

39. 发明授权

US07858982B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07858982B2
公开(公告)日：2010-12-28
申请号：US11215067
申请日：2005-08-29
申请人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun Lee , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L29/04
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

40. 发明授权

US07741641B2 TFT substrate and display device having the same 失效
标题翻译： TFT基板和具有该TFT基板的显示装置
公开(公告)号：US07741641B2
公开(公告)日：2010-06-22
申请号：US11371057
申请日：2006-03-08
申请人： Yang-Ho Bae , Chang-Oh Jeong , Min-Seok Oh , Je-Hun Lee , Beom-Seok Cho
发明人： Yang-Ho Bae , Chang-Oh Jeong , Min-Seok Oh , Je-Hun Lee , Beom-Seok Cho
IPC分类号： H01L29/43 , H01L29/786
CPC分类号： H01L29/4908 , H01L27/124 , H01L29/458
摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.
摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。栅极布线包括栅极线和栅电极。栅极绝缘层形成在基底基板上以覆盖栅极布线。活化层形成在栅绝缘层上。氧化阻挡层形成在活化层上。数据线包括数据线，源电极和漏电极。源电极和漏电极设置在氧化阻挡层上，因此降低用于导通TFT的导通电流（“Ion”），并且由于氧化阻挡层而增加关闭TFT的截止电流（“Ioff”），阻挡层。

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