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    • 31. 发明授权
    • Intelligent dead time control
    • 智能死区时间控制
    • US07683594B2
    • 2010-03-23
    • US11757181
    • 2007-06-01
    • Seungbeom Kevin KimTodd VaccaJason Zhang
    • Seungbeom Kevin KimTodd VaccaJason Zhang
    • G05F1/40
    • H02M7/219H02M1/38
    • A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.
    • 一种用于降低开关级的同步整流器中的开关损耗的电路,包括耦合在开关节点处的高侧控制晶体管和低侧同步晶体管,所述开关级接收输入电压并在输出端提供受控的输出电压 节点。 该电路包括用于感测低侧同步晶体管的栅极端处的第一信号的波形边缘的第一电路部分和用于确定第一信号的波形边缘与第一电压的波形边缘之间的延迟的第一电压 ; 以及第二电路部分,用于校准第一信号和第一电压,以使第一信号的波形边缘和第一电压的波形边缘与可选的偏移对准,以实现最小的功率损耗。
    • 35. 发明申请
    • INTELLIGENT DEAD TIME CONTROL
    • 智能死亡时间控制
    • US20080298101A1
    • 2008-12-04
    • US11757181
    • 2007-06-01
    • Seungbeom Kevin KimTodd VaccaJason Zhang
    • Seungbeom Kevin KimTodd VaccaJason Zhang
    • H02M7/04H02M7/217
    • H02M7/219H02M1/38
    • A circuit for reducing switching losses in a synchronous rectifier of a switching stage including a high-side control transistor and a low-side synchronous transistor coupled at a switching node, the switching stage receiving an input voltage and providing a controlled output voltage at an output node. The circuit including a first circuit portion for sensing waveshape edges of a first signal at a gate terminal of the low-side synchronous transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage; and a second circuit portion for calibrating the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to achieve minimal power loss.
    • 一种用于降低开关级的同步整流器中的开关损耗的电路,包括耦合在开关节点处的高侧控制晶体管和低侧同步晶体管,所述开关级接收输入电压并在输出端提供受控的输出电压 节点。 该电路包括用于感测低侧同步晶体管的栅极端处的第一信号的波形边缘的第一电路部分和用于确定第一信号的波形边缘与第一电压的波形边缘之间的延迟的第一电压 ; 以及第二电路部分,用于校准第一信号和第一电压,以使第一信号的波形边缘和第一电压的波形边缘与可选的偏移对准,以实现最小的功率损耗。