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31. 发明授权

US06591321B1 Multiprocessor system bus protocol with group addresses, responses, and priorities 有权
标题翻译：具有组地址，响应和优先级的多处理器系统总线协议
公开(公告)号：US06591321B1
公开(公告)日：2003-07-08
申请号：US09437200
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system. All of the bus accessible memory devices on the cache bus line send snoop responses in response to the bus master signal based on the designated snoop response group. The snoop responses are sent to the combined response logic system. A combined response by the combined response logic system is determined based on the appropriate combined response encoding logic determined by the designated and latched snoop response group. The combined response is sent to all of the bus accessible memory devices on the cache bus line.
摘要翻译：一种用于处理和处理处理器请求的多处理器系统总线协议系统和方法，所述多处理器系统具有被窥探的多个总线可访问存储器件。至少有一条总线。提供了来自总线可访问存储器设备的不同类型的窥探响应的侦听响应组。在每个窥探响应组中提供不同的传输类型。指定提供总线主机信号的总线主设备。总线主设备接收处理器请求。根据处理器请求适当地指定其中一个侦听响应组和传输类型之一。总线主机信号由侦听响应组，传输类型，有效请求信号和高速缓存线地址来制定。总线主机信号被发送到高速缓存总线上的所有总线可访问存储器件和组合响应逻辑系统。基于指定的窥探响应组，高速缓存总线上的所有总线可访问存储器件响应于总线主机信号发送窥探响应。侦听响应被发送到组合的响应逻辑系统。基于由指定和锁存的窥探响应组确定的适当的组合响应编码逻辑来确定组合响应逻辑系统的组合响应。组合的响应被发送到高速缓存总线上的所有总线可访问存储器件。

32. 发明授权

US06519665B1 Multi-node data processing system and communication protocol in which a stomp signal is propagated to cancel a prior request 失效
标题翻译：多节点数据处理系统和传播踩踏信号以消除先前请求的通信协议
公开(公告)号：US06519665B1
公开(公告)日：2003-02-11
申请号：US09436900
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F15/16
摘要： A data processing system includes at least first and second nodes and a segmented interconnect having coupled first and second segments. The first node includes the first segment and first and second agents coupled to the first segment, and the second node includes the second segment and a third agent coupled to the second segment. The first node further includes cancellation logic that, in response to the first agent issuing a request on the segmented interconnect that propagates from the first segment to the second segment and the second agent indicating ability to service the request, sends a cancellation message to the third agent instructing the third agent to ignore the request.
摘要翻译：数据处理系统至少包括第一和第二节点以及具有耦合的第一和第二段的分段互连。第一节点包括第一段和耦合到第一段的第一和第二代理，并且第二节点包括第二段和耦合到第二段的第三代理。第一节点还包括消除逻辑，响应于第一代理在从第一段传播到第二段的分段互连上发出请求，并且第二代理指示服务该请求的能力，向第三代发送取消消息代理指示第三代理人忽略该请求。

33. 发明授权

US06405289B1 Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response 失效
标题翻译：多处理器系统，其中作为最高点的一致性的缓存由窥探响应指示
公开(公告)号：US06405289B1
公开(公告)日：2002-06-11
申请号：US09437196
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/2542
摘要： A method of maintaining cache coherency, by designating one cache that owns a line as a highest point of coherency (HPC) for a particular memory block, and sending a snoop response from the cache indicating that it is currently the HPC for the memory block and can service a request. The designation may be performed in response to a particular coherency state assigned to the cache line, or based on the setting of a coherency token bit for the cache line. The processing units may be grouped into clusters, while the memory is distributed using memory arrays associated with respective clusters. One memory array is designated as the lowest point of coherency (LPC) for the memory block (i.e., a fixed assignment) while the cache designated as the HPC is dynamic (i.e., changes as different caches gain ownership of the line). An acknowledgement snoop response is sent from the LPC memory array, and a combined response is returned to the requesting device which gives priority to the HPC snoop response over the LPC snoop response.
摘要翻译：通过将一个具有一行的高速缓存指定为特定存储器块的最高一致性（HPC），以及从高速缓存指示其当前是存储器块的HPC的高速缓存发送侦听响应的方法来维持高速缓存一致性的方法，以及可以服务请求。可以响应于分配给高速缓存行的特定一致性状态，或者基于高速缓存行的相关性令牌位的设置来执行指定。处理单元可以被分组成群集，而存储器是使用与相应簇相关联的存储器阵列分布的。一个存储器阵列被指定为存储器块的一致性（LPC）的最低点（即，固定分配），而指定为HPC的缓存是动态的（即，随着不同的高速缓存获得线的所有权而改变）。从LPC存储器阵列发送确认窥探响应，并且将组合的响应返回给请求设备，该请求设备通过LPC窥探响应优先考虑HPC侦听响应。

34. 发明授权

US06393528B1 Optimized cache allocation algorithm for multiple speculative requests 失效
标题翻译：针对多个推测请求的优化缓存分配算法
公开(公告)号：US06393528B1
公开(公告)日：2002-05-21
申请号：US09345714
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/127
摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hiearchy and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.
摘要翻译：公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器hiearchy请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已被满足，则包含先前预取值中的一个的高速缓存行中的高速缓存行被分配用于接收另一个预取值。

35. 发明授权

US6101563A Configuration access system 失效
标题翻译：配置接入系统
公开(公告)号：US6101563A
公开(公告)日：2000-08-08
申请号：US80031
申请日：1998-05-15
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Alan Riek
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , Kenneth Alan Riek
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/404
摘要： A methodology and implementing system are provided in which PCI system configuration data is made available to a host X86 system CPU through an intermediate PowerPC system. A bus converter circuit connected between the X86 bus and the PowerPC bus is effective to translate configuration addresses between the X86 and the PowerPC system. A PCI host bridge arrangement includes a primary PCI host bridge circuit and a plurality of secondary peer PCI host bridge circuits. The primary host bridge circuit is effective to process configuration data requests from the bus converter circuit which are directed to any of the secondary PCI host bridge circuits.
摘要翻译：提供了一种方法和实现系统，其中PCI系统配置数据通过中间PowerPC系统可用于主机X86系统CPU。连接在X86总线和PowerPC总线之间的总线转换器电路有效地在X86和PowerPC系统之间转换配置地址。 PCI主机桥机构包括主PCI主桥电路和多个次要对等PCI主桥电路。主主机桥电路有效地处理来自总线转换器电路的配置数据请求，其指向任何辅助PCI主机桥电路。

36. 发明授权

US06601145B2 Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls 失效
公开(公告)号：US06601145B2
公开(公告)日：2003-07-29
申请号：US09749348
申请日：2000-12-27
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized. The invention is not limited to any particular type of instruction, and the synchronization functionality may be hardware or software programmable.

37. 发明授权

US06546470B1 Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation 失效
标题翻译：用于有限带宽窥探者的多处理器系统侦听调度机制，具有实现目录
公开(公告)号：US06546470B1
公开(公告)日：2003-04-08
申请号：US09749349
申请日：2001-03-12
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Guy Lynn Guthrie , Jody B. Joyner
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized. The invention is not limited to any particular type of instruction, and the synchronization functionality may be hardware or software programmable.
摘要翻译：一种多处理器计算机系统，其中高速缓存的窥探操作被同步以允许在基于高速缓存已被同步的特定方式选择的周期期间发出高速缓存操作。每个缓存控制器都知道何时发生这些同步的窥探任务，并且可以针对某些对窥探重试敏感的请求（如kill-type操作）来定位这些周期。同步可以为具有多个互连总线的系统建立优先级方案，或者可以同步窥探者目录的DRAM存储器的刷新周期。在本发明的另一方面，创建窗口，在该窗口期间，目录将不会接收写入操作（即，该目录仅被保留用于仅读操作）。本发明可以在缓存层级中实现，该缓存层级提供了布置在存储体中的存储体，存储体同样地同步。本发明不限于任何特定类型的指令，并且同步功能可以是硬件或软件可编程的。

38. 发明授权

US06519649B1 Multi-node data processing system and communication protocol having a partial combined response 失效
标题翻译：多节点数据处理系统和具有部分组合响应的通信协议
公开(公告)号：US06519649B1
公开(公告)日：2003-02-11
申请号：US09436899
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F12/0813
摘要： A data processing system includes an interconnect and first and second nodes, coupled to the interconnect, that each include at least one agent. Each agent within the first and second nodes outputs a snoop response in response to snooping a transaction on the interconnect. Utilizing the snoop response of each agent within the first node, first response logic within the first node produces a first cumulative combined response. This first cumulative combined response is then combined by second response logic in the second node with the snoop response of each agent in the second node to produce a second cumulative combined response. After a complete combined response is obtained in this manner, the complete combined response is distributed to all nodes so that each agent can determine its response, if any, to the transaction.
摘要翻译：数据处理系统包括互连以及耦合到互连的第一和第二节点，每个包括至少一个代理。第一和第二节点内的每个代理响应于窥探互连上的事务而输出一个窥探响应。利用第一节点内的每个代理的窥探响应，第一节点内的第一响应逻辑产生第一累积组合响应。然后，该第一累积组合响应由第二节点中的第二响应逻辑与第二节点中每个代理的窥探响应组合以产生第二累积组合响应。在以这种方式获得完整的组合响应之后，完整的组合响应被分配给所有节点，使得每个代理可以确定其对事务的响应（如果有的话）。

39. 发明授权

US06470427B1 Programmable agent and method for managing prefetch queues 有权
标题翻译：用于管理预取队列的可编程代理和方法
公开(公告)号：US06470427B1
公开(公告)日：2002-10-22
申请号：US09436373
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A programmable agent and method for managing prefetch queues provide dynamically configurable handling of priorities in a prefetching subsystem for providing look-ahead memory loads in a computer system. When it's queues are at capacity an agent handling prefetches from memory either ignores new requests, forces the new requests to retry or cancels a pending request in order to perform the new request. The behavior can be adjusted under program control by programming a register, or the control may be coupled to a load pattern analyzer. In addition, the behavior with respect to new requests can be set to different types depending on a phase of a pending request.
摘要翻译：用于管理预取队列的可编程代理和方法为预取子系统中的优先级提供动态可配置的处理，以在计算机系统中提供先行存储器负载。当队列处理能力时，代理处理来自内存的预取将忽略新的请求，强制新的请求重试或取消挂起的请求，以执行新的请求。通过对寄存器进行编程，可以在程序控制下调整行为，或者控制可以耦合到负载模式分析器。此外，根据待处理请求的阶段，关于新请求的行为可以被设置为不同的类型。

40. 发明授权

US06360299B1 Extended cache state with prefetched stream ID information 失效
标题翻译：扩展缓存状态与预取流ID信息
公开(公告)号：US06360299B1
公开(公告)日：2002-03-19
申请号：US09345644
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/121 , G06F2212/6028
摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.
摘要翻译：公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取值。

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