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31. 发明申请

US20150339124A1 SYSTEM AND METHOD FOR SELECTIVELY ALLOCATING ENTRIES AT A BRANCH TARGET BUFFER 有权
标题翻译：在分支目标缓存器中选择分配入口的系统和方法
公开(公告)号：US20150339124A1
公开(公告)日：2015-11-26
申请号：US14282290
申请日：2014-05-20
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.
摘要翻译：在数据处理系统处接收分支指令和对应的分支指令地址。接收到第一个值，并将其与分支指令地址的一部分进行比较。基于比较的结果，选择性地分配与分支指令对应的分支目标缓冲器中的条目。

32. 发明申请

US20140068346A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20140068346A1
公开(公告)日：2014-03-06
申请号：US13598240
申请日：2012-08-29
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F11/34
CPC分类号： G06F11/3636
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO追查观察点的发生导致跟踪信息在跟踪信息已被传送到跟踪分析器之前被从跟踪FIFO刷新。

33. 发明授权

US08364937B2 Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor 有权
标题翻译：在可配置流水线处理器中，在奇偶校验保护模式的第二个执行阶段执行未对齐的负载相关指令
公开(公告)号：US08364937B2
公开(公告)日：2013-01-29
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a load instruction and a data-dependent instruction to the instruction pipeline. Based on an operating mode, such as ECC mode or parity mode, the data-dependent instruction may execute in either the first of the second instruction pipeline stage. Further, the execution of the data-dependent instruction may depend on whether the most recently executed instruction was misaligned.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括向指令流水线提供加载指令和数据相关指令。基于诸如ECC模式或奇偶校验模式的操作模式，数据相关指令可以在第二指令流水线级中的第一个中执行。此外，数据相关指令的执行可能取决于最近执行的指令是否不对齐。

34. 发明申请

US20090222648A1 SELECTIVE POSTPONEMENT OF BRANCH TARGET BUFFER (BTB) ALLOCATION 有权
标题翻译：分支目标缓冲区（BTB）分配的选择性支持
公开(公告)号：US20090222648A1
公开(公告)日：2009-09-03
申请号：US12040204
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3814 , G06F9/3844
摘要： A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.
摘要翻译：系统和方法提供分支目标缓冲区（BTB）分配。当接收到分支指令时，确定与分支指令对应的分支目标地址。确定分支目标地址是否当前存储在分支目标缓冲器（BTB）中。当分支目标地址当前不存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目以接收分支目标地址。使用分支目标缓冲器中的所识别的条目中的字段中的值（诸如推迟标志（PF））来选择性地覆盖由预定分支目标缓冲器分配标准定义的替换决策。在一种形式中，如果采取分支，则响应于确定所识别的条目中的字段中的值具有预定值，将所标识的条目替换为分支目标地址。

35. 发明申请

US20090187789A1 METHOD AND APPARATUS FOR HANDLING SHARED HARDWARE AND SOFTWARE DEBUG RESOURCE EVENTS IN A DATA PROCESSING SYSTEM 有权
标题翻译：在数据处理系统中处理共享硬件和软件调试资源事件的方法和装置
公开(公告)号：US20090187789A1
公开(公告)日：2009-07-23
申请号：US12016664
申请日：2008-01-18
申请人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
发明人： William C. Moyer , Jimmy Gumulja , Jeffrey W. Scott
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.
摘要翻译：对于一些数据处理系统，重要的是能够处理由共同的一组调试资源生成的重叠调试事件，这些调试资源试图引起异常处理和调试模式输入。但是，异常处理和调试模式条目通常具有冲突的要求。在一个实施例中，最初给出软件调试事件的异常优先级处理。执行正常状态保存，并且提取调试异常处理程序的第一条指令，但不执行。优先级然后从软件调试事件切换到硬件调试事件，并且进入调试停止状态。一旦硬件调试事件的处理完成，优先级将返回到软件调试事件，并执行调试异常处理程序。

36. 发明授权

US07124281B1 Processing system having sequential address indicator signals 有权
标题翻译：具有顺序地址指示符信号的处理系统
公开(公告)号：US07124281B1
公开(公告)日：2006-10-17
申请号：US09667122
申请日：2000-09-21
申请人： William C. Moyer , Jeffrey W. Scott , Brett W. Murdock
发明人： William C. Moyer , Jeffrey W. Scott , Brett W. Murdock
IPC分类号： G06F9/00
CPC分类号： G06F13/28
摘要： Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.
摘要翻译：本发明的实施例涉及具有顺序地址指示符信号的处理器，也称为序列信号，用于指示何时访问的地址是顺序的。一个实施例涉及一种用于访问具有用于向存储器提供当前地址和前一地址的地址总线的存储器的处理系统，数据总线，执行单元和解码控制单元。该处理系统还包括一个提取单元，耦合到执行单元，解码控制单元，地址总线和数据总线，用于产生一个第一序列信号，当被否定时指示当前地址可能不与先前的地址，当被否定时指示当前地址不与先前地址顺序的第二序列信号，以及当被否定时的第三序列信号指示当前地址（如果是指令地址）不是与先前地址相连那是一个指示地址。

37. 发明授权

US06378022B1 Method and apparatus for processing interruptible, multi-cycle instructions 有权
标题翻译：用于处理可中断，多周期指令的方法和装置
公开(公告)号：US06378022B1
公开(公告)日：2002-04-23
申请号：US09335105
申请日：1999-06-17
申请人： William C. Moyer , Jeffrey W. Scott , Michael D. Fitzsimmons
发明人： William C. Moyer , Jeffrey W. Scott , Michael D. Fitzsimmons
IPC分类号： G06F1324
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/30065 , G06F9/3859 , G06F9/3869 , G06F13/24
摘要： A method and apparatus for processing multi-cycle instructions. In one embodiment, the method includes beginning execution of a multi-cycle instruction by the processing device, and, during execution of the multi-cycle instruction, comparing a threshold value to a count value that indicates a number of remaining cycles before completion of the multi-cycle instruction. In one embodiment, the apparatus includes a processing unit. The processing unit includes an interrupt control module that has an interrupt request signal input and a second input to receive a multi-cycle instruction interrupt signal. The multi-cycle instruction interrupt signal is to indicate an interruptible interval when an interrupt of a multi-cycle instruction is permitted prior to completion of the multi-cycle instruction.
摘要翻译：一种用于处理多周期指令的方法和装置。在一个实施例中，该方法包括由处理装置开始执行多周期指令，并且在执行多周期指令期间，将阈值与表示完成之前的剩余周期数的计数值进行比较多周期指令在一个实施例中，该装置包括处理单元。处理单元包括具有中断请求信号输入的中断控制模块和用于接收多周期指令中断信号的第二输入。多周期指令中断信号是指示在多周期指令完成之前允许多周期指令的中断的可中断间隔。

38. 发明授权

US09304773B2 Data processor having dynamic control of instruction prefetch buffer depth and method therefor 有权
标题翻译：数据处理器具有指令预取缓冲区深度的动态控制及其方法
公开(公告)号：US09304773B2
公开(公告)日：2016-04-05
申请号：US11385463
申请日：2006-03-21
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).
摘要翻译：数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。预取缓冲器（112）具有多条线。预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。获取控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并且响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度数据处理器（102）。

39. 发明授权

US09223678B2 Data processor device having a debug control module which selectively modifies trace messages 有权
标题翻译：具有调试控制模块的数据处理器设备，其选择性地修改跟踪消息
公开(公告)号：US09223678B2
公开(公告)日：2015-12-29
申请号：US13955102
申请日：2013-07-31
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F11/30 , G06F11/36
CPC分类号： G06F11/36 , G06F11/3072 , G06F11/3082 , G06F11/3636
摘要： Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.
摘要翻译：当检测到用于调试计算机处理系统的观察点事件的发生时，当所述至少一个消息的特性与指定的特性匹配时，跟踪消息缓冲器中的至少一个消息的至少一部分被刷新。

40. 发明授权

US09069896B2 Data processor device for handling a watchpoint and method thereof 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US09069896B2
公开(公告)日：2015-06-30
申请号：US13598240
申请日：2012-08-29
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/3636
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO追查观察点的发生导致跟踪信息在跟踪信息已被传送到跟踪分析器之前被从跟踪FIFO刷新。

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