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31. 发明授权

US07148578B2 Semiconductor multi-chip package 有权
标题翻译：半导体多芯片封装
公开(公告)号：US07148578B2
公开(公告)日：2006-12-12
申请号：US10651813
申请日：2003-08-28
申请人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
发明人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L23/495 , H01L23/525 , H01L25/065
CPC分类号： H01L24/05 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06558 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
摘要翻译：半导体芯片包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体基板。在半导体衬底上形成接合焊盘布线图形。焊盘重排图案电连接到接合焊盘布线图案。垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。接合焊盘布线图形基本上形成在半导体衬底的中心区域中。因此，利用本发明的实施例，由此可以大大减小总体芯片尺寸，并且可以制造MCP而没有上述问题。

32. 发明申请

US20050224948A1 Semiconductor device package having buffered memory module and method thereof 有权
标题翻译：具有缓冲存储器模块的半导体器件封装及其方法
公开(公告)号：US20050224948A1
公开(公告)日：2005-10-13
申请号：US11033845
申请日：2005-01-13
申请人： Jong-Joo Lee , Young-Hee Song
发明人： Jong-Joo Lee , Young-Hee Song
IPC分类号： H01L23/50 , G11C11/00 , H01L23/02 , H05K1/18
CPC分类号： H05K1/181 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/15311 , H01L2924/19105 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611 , H01L2924/00014 , H01L2924/00
摘要： A method and apparatus of fabricating a semiconductor device are disclosed. The semiconductor device may include a buffer chip package having a buffer chip mounted on a buffer chip substrate and at least one memory package mounted on the buffer chip substrate, wherein the at least one memory package may include a plurality of memory chips. Further, the buffer chip package may have a plurality of external connection terminals.
摘要翻译：公开了制造半导体器件的方法和装置。半导体器件可以包括缓冲芯片封装，其具有安装在缓冲芯片基板上的缓冲芯片和安装在缓冲芯片基板上的至少一个存储器封装，其中所述至少一个存储器封装可以包括多个存储器芯片。此外，缓冲芯片封装可以具有多个外部连接端子。

33. 发明授权

US07786594B2 Wafer level stack structure for system-in-package and method thereof 有权
标题翻译：用于系统级封装的晶圆级堆叠结构及其方法
公开(公告)号：US07786594B2
公开(公告)日：2010-08-31
申请号：US11822630
申请日：2007-07-09
申请人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
发明人： Kang-Wook Lee , Se-Yong Oh , Young-Hee Song , Gu-Sung Kim
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589 , H01L2924/00 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
摘要翻译：一种晶片级堆叠结构，包括包括第一芯片尺寸的至少一个第一器件芯片的第一晶片，其中每个第一器件芯片包含第一多个输入/输出（I / O）焊盘，第二晶片包括至少一个第二芯片尺寸小于第一芯片尺寸的第二器件芯片，其中每个第二器件芯片包含第二多个I / O焊盘，其中所述至少一个第二器件芯片增加到所述第一芯片尺寸，其中所述第一晶片并且第二晶片被堆叠，并且其中第一晶片和第二晶片彼此耦合。一种系统级封装，包括晶片级堆叠结构，其包括具有第一多个输入/输出（I / O）焊盘的至少一个第一器件芯片和至少一个具有第二多个I / O焊盘的第二器件芯片，以及与晶片级堆叠结构连接的公共电路板。

34. 发明授权

US07547977B2 Semiconductor chip having bond pads 有权
标题翻译：具有接合垫的半导体芯片
公开(公告)号：US07547977B2
公开(公告)日：2009-06-16
申请号：US11616850
申请日：2006-12-27
申请人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
发明人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
IPC分类号： H01L23/52 , H01L23/50 , H01L23/495 , H01L23/525 , H01L25/065
CPC分类号： H01L24/05 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06558 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.
摘要翻译：在一个实施例中，半导体芯片具有一个或多个外围接合焊盘。半导体芯片包括具有彼此相邻的单元区域和外围电路区域的半导体衬底; 形成在半导体衬底的周边区域的至少一部分上的接合焊盘布线图案; 形成在所述接合焊盘布线图案上的钝化层和所述半导体基板的暴露部分; 衬垫重排图案，设置在钝化层上并电连接到接合焊盘布线图案; 以及形成在垫重排图案上的绝缘层。绝缘层在其中具有露出焊盘重排图案的一部分以限定接合焊盘的开口。接合焊盘设置在电池区域的至少一部分上。

35. 发明授权

US07368821B2 BGA semiconductor chip package and mounting structure thereof 失效
标题翻译： BGA半导体芯片封装及其安装结构
公开(公告)号：US07368821B2
公开(公告)日：2008-05-06
申请号：US11231751
申请日：2005-09-22
申请人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
发明人： Sang-Young Kim , Jin-Ho Kim , Hee-Jin Park , Young-Hee Song , Tae-Sung Yoon
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H05K3/303 , H05K3/3436 , H05K3/3452 , H05K2201/094 , H05K2201/09781 , H05K2201/10734 , H05K2201/2036 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.
摘要翻译：在本发明的示例性实施例中，BGA半导体芯片封装的结构包括具有第一和第二表面的衬底，具有多个焊盘的半导体芯片，并且安装在衬底的第一表面上，以及多个入/ （I / O）焊球和设置在基板的第二表面上的虚拟焊球，其中I / O焊球电连接到半导体芯片，并且虚拟焊球与半导体芯片电隔离，并且 I / O焊球和虚拟焊球具有相同的球尺寸和球间距，并均匀地设置在基板的第二表面上。

36. 发明申请

US20070108633A1 SEMICONDUCTOR CHIP HAVING BOND PADS 有权
标题翻译：具有粘结垫的半导体芯片
公开(公告)号：US20070108633A1
公开(公告)日：2007-05-17
申请号：US11616857
申请日：2006-12-27
申请人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
发明人： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32245 , H01L2224/48 , H01L2224/48091 , H01L2224/48095 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/48227 , H01L2924/00 , H01L2924/00012 , H01L2224/32225 , H01L2224/45099
摘要： A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
摘要翻译：半导体芯片包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体基板。在半导体衬底上形成接合焊盘布线图形。焊盘重排图案电连接到接合焊盘布线图案。垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。因此，利用本发明的实施例，由此可以大大减小总体芯片尺寸，并且可以制造MCP而没有上述问题。

37. 发明授权

US07071555B2 Ball grid array package stack 失效
公开(公告)号：US07071555B2
公开(公告)日：2006-07-04
申请号：US10691240
申请日：2003-10-21
申请人： Jung-Jin Kim , Young-Hee Song , Dong-Ho Lee
发明人： Jung-Jin Kim , Young-Hee Song , Dong-Ho Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/45144 , H01L2224/48227 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit substrate is folded in two. In the lower BGA package, an IC chip is attached on and electrically connected to a top surface of the first portion, and external connection terminals such as solder balls are formed on a bottom surface of the first portion. The top surface of the first portion is covered with a molding resin to protect the chip, and the third portion is placed on an upper surface of the molding resin. The upper BGA package is constructed in a similar manner to the lower BGA package as described above. For stacking, the interconnection terminals of the upper BGA package are joined and electrically connected to the third portion of the foldable circuit substrate of the lower BGA package.

38. 发明申请

US20050054155A1 Semiconductor device having fuse circuit on cell region and method of fabricating the same 有权
标题翻译：在单元区域具有熔丝电路的半导体器件及其制造方法
公开(公告)号：US20050054155A1
公开(公告)日：2005-03-10
申请号：US10971374
申请日：2004-10-22
申请人： Young-Hee Song , Ill-Heung Choi , Min-Young Son , Min-Sang Park
发明人： Young-Hee Song , Ill-Heung Choi , Min-Young Son , Min-Sang Park
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/82 , H01L23/52 , H01L23/525 , H01L27/02 , H01L27/10 , H01L27/108 , G11C5/00 , H01L21/336 , H01L21/8234 , H01L21/8244
CPC分类号： H01L24/05 , H01L23/5258 , H01L24/03 , H01L24/45 , H01L24/48 , H01L27/10897 , H01L2224/04042 , H01L2224/05155 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/451 , H01L2224/45144 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/12042 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, capable of improving integration density and solving problems that may occur in a laser repair process, and a method of fabricating the same are provided. A fuse circuit is formed in a cell region, not in a peripheral region, and thus it is possible to reduce the size of a semiconductor chip.
摘要翻译：提供能够提高集成密度并解决激光修复过程中可能发生的问题的半导体器件及其制造方法。在单元区域中形成熔丝电路，而不是在周边区域，因此可以减小半导体芯片的尺寸。

39. 发明授权

US06724074B2 Stack semiconductor chip package and lead frame 失效
标题翻译：堆叠半导体芯片封装和引线框架
公开(公告)号：US06724074B2
公开(公告)日：2004-04-20
申请号：US10289668
申请日：2002-11-06
申请人： Young-Hee Song , Hai-Jeong Sohn , Ill-Heung Choi , Sung-Ho Hong
发明人： Young-Hee Song , Hai-Jeong Sohn , Ill-Heung Choi , Sung-Ho Hong
IPC分类号： H01L23495
CPC分类号： H01L23/49575 , H01L23/4951 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2924/00014 , H01L2924/01055 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： A stack package has a lead frame and first and second stacked chips. The lead frame comprises first and second lead groups respectively corresponding to the first and second chips and a plurality of external connection terminals for electrically interconnecting the first and second chips to an external device. Each of the first and second chips has its own common and independent electrode pads, and each of the first and second lead groups has its own common and independent leads. The common leads and the common electrode pads are for address and control signals to and from the first and second chips, and the independent leads and the independent electrode pads are for data input and output to and from the first and second chips. The common leads of the first lead group and the common leads of the second lead group are commonly interconnected to be connected to an identical external connection terminal of the plurality of external connection terminals, and the independent leads of the first lead group and the independent leads of the second lead group are connected to different external connection terminal. The first and second chips are disposed symmetrically with respect to the common leads and face each other with their backsides. The stack package can be implemented by using two memory devices and two lead frames of LOC type and can increase two times the memory capacity and bit structure.
摘要翻译：堆叠包装具有引线框架和第一和第二堆叠芯片。引线框架包括分别对应于第一和第二芯片的第一和第二引线组以及用于将第一和第二芯片电连接到外部设备的多个外部连接端子。第一和第二芯片中的每一个具有其自己的共同和独立的电极焊盘，并且第一和第二引线组中的每一个具有其自己的共同和独立引线。公共引线和公共电极焊盘用于来自第一和第二芯片的地址和控制信号，独立引线和独立电极焊盘用于数据输入和输出到第一和第二芯片。第一引线组和第二引线组的公共引线的公共引线通常互连以连接到多个外部连接端子的相同的外部连接端子，并且第一引线组和独立引线的独立引线的第二引线组连接到不同的外部连接端子。第一芯片和第二芯片相对于公共引线对称地设置并且以它们的背面彼此面对。可以通过使用两个存储器件和LOC型的两个引线框来实现堆栈封装，并且可以增加存储器容量和位结构的两倍。

40. 发明授权

US06483038B2 Memory card 有权
公开(公告)号：US06483038B2
公开(公告)日：2002-11-19
申请号：US09865045
申请日：2001-05-23
申请人： Joon-ki Lee , Woong-ky Ha , Young-Hee Song , Young-shin Kwon
发明人： Joon-ki Lee , Woong-ky Ha , Young-Hee Song , Young-shin Kwon
IPC分类号： H05K103
CPC分类号： H01L23/5388 , G06K19/07743 , H01L23/10 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2924/01078 , H01L2924/01079 , H01L2924/181 , H01L2924/19041 , Y10S439/946 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides a memory card having a reduced size as much as that of the package. The memory card includes electrical contact pads disposed in a single row on one end of the memory card. The memory card further comprises a card base and a semiconductor package. The card base has a first surface and a second surface, the first surface having a cavity formed thereon. The semiconductor package comprises a substrate, memory chips, and a molding resin layer, and is mounted on the cavity so that the external contact pads are exposed. Circuit wirings are formed on an inner surface of the substrate and electrically connected to the external contact pads that are formed on an outer surface of the substrate.

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