专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07011911B2 Mask for polycrystallization and method of manufacturing thin film transistor using polycrystallization mask 有权
标题翻译：多结晶掩模和使用多结晶掩模制造薄膜晶体管的方法
公开(公告)号：US07011911B2
公开(公告)日：2006-03-14
申请号：US10663081
申请日：2003-09-16
申请人： Hyun-Jae Kim , Sook-Young Kang , Myung-Koo Kang
发明人： Hyun-Jae Kim , Sook-Young Kang , Myung-Koo Kang
IPC分类号： G03F9/00
CPC分类号： H01L29/66757 , H01L29/78675
摘要： In a method of manufacturing a thin film transistor according to the present invention, an amorphous silicon thin film is firstly formed on an insulating substrate and a planarization layer is formed thereon. Thereafter, the amorphous silicon thin film is crystallized by a solidification process using a laser-irradiation to form a polysilicon thin film. Next, the polysilicon thin film and the planarization layer are patterned to form a semiconductor layer, and a gate insulating layer covering the semiconductor layer is formed. Then, a gate electrode is formed on the gate insulating layer opposite the semiconductor layer. Next, impurities are implanted into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode, and a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively, are formed.
摘要翻译：在本发明的薄膜晶体管的制造方法中，首先在绝缘基板上形成非晶硅薄膜，在其上形成平坦化层。此后，通过使用激光照射的固化工艺使非晶硅薄膜结晶，形成多晶硅薄膜。接下来，对多晶硅薄膜和平坦化层进行构图以形成半导体层，并且形成覆盖半导体层的栅极绝缘层。然后，在与半导体层相对的栅极绝缘层上形成栅电极。接下来，将杂质注入到半导体层中以形成相对于栅极彼此相对的源极区域和漏极区域，并且分别与源极区域和漏极区域电连接的源极电极和漏极电极是形成。

32. 发明授权

US06906349B2 Polysilicon thin film transistor array panel and manufacturing method thereof 有权
公开(公告)号：US06906349B2
公开(公告)日：2005-06-14
申请号：US10752510
申请日：2004-01-08
申请人： Hyun-Jae Kim , Sook-Young Kang , Dong-Byum Kim , Su-Gyeong Lee , Myung-Koo Kang
发明人： Hyun-Jae Kim , Sook-Young Kang , Dong-Byum Kim , Su-Gyeong Lee , Myung-Koo Kang
IPC分类号： H01L51/50 , G09F9/30 , H01L21/00 , H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L27/32 , H01L29/04 , H01L29/786 , H01L29/788 , H01L31/036 , H01L31/0392 , H01L31/20 , H05B33/14
CPC分类号： H01L21/02678 , C30B13/24 , C30B29/06 , H01L21/02532 , H01L21/02595 , H01L21/2026 , H01L27/1229 , H01L27/1285 , H01L27/1296 , Y10T428/24273
摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: depositing an amorphous silicon layer on an insulating substrate; converting the amorphous silicon layer to a polysilicon layer by a plurality of laser shots using a mask; forming a gate insulating layer on the polysilicon layer; forming a plurality of gate lines on the gate insulating layer; forming a first interlayer insulating layer on the gate lines; forming a plurality of data lines on the first interlayer insulating layer; forming a second interlayer insulating layer on the data lines; and forming a plurality of pixel electrodes on the second interlayer insulating layer, wherein the mask comprises a plurality of transmitting areas and a plurality of blocking areas arranged in a mixed manner.

33. 发明申请

US20050079693A1 Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask 有权
标题翻译：用于结晶多晶硅的掩模和使用掩模形成薄膜晶体管的方法
公开(公告)号：US20050079693A1
公开(公告)日：2005-04-14
申请号：US10495673
申请日：2002-01-24
申请人： Myung-Koo Kang , Hyun-Jae Kim , Sook-Young Kang
发明人： Myung-Koo Kang , Hyun-Jae Kim , Sook-Young Kang
IPC分类号： G02F1/1368 , H01L21/20 , H01L21/336 , H01L29/786
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/0268 , H01L21/2026 , H01L29/66757 , H01L29/78675 , Y10S260/35
摘要： A mask for forming polysilicon has a first slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a second slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, a third slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width, and a fourth slit region where a plurality of horizontal slit patterns are arranged in the vertical direction while bearing the same width. The slit patterns arranged at the first to fourth slit regions are sequentially enlarged in width in the horizontal direction in multiple proportion to the width d of the slit pattern at the first slit region. The centers of the slit patterns arranged at the first to fourth slit regions in the horizontal direction are placed at the same line. The slit patterns arranged at the respective slit regions in the vertical direction are spaced from each other with a distance of 8*d. Alternatively, the first to fourth slit regions may be arranged in reverse order, or in the vertical direction.
摘要翻译：用于形成多晶硅的掩模具有第一狭缝区域，其中垂直方向上布置多个水平狭缝图案，同时承载相同的宽度，在垂直方向上布置多个水平狭缝图案的第二狭缝区域，同时承载相同的宽度宽度，在垂直方向上布置多个水平狭缝图案同时具有相同宽度的第三狭缝区域，以及沿垂直方向布置多个水平狭缝图案的第四狭缝区域，同时承载相同的宽度。布置在第一至第四狭缝区域的狭缝图案在第一狭缝区域上与狭缝图案的宽度d成一定比例地沿水平方向的宽度依次增大。沿水平方向布置在第一至第四狭缝区域处的狭缝图案的中心位于相同的线上。在垂直方向的各个狭缝区域上排列的狭缝图案彼此间隔8 * d。或者，第一至第四狭缝区域可以以相反的顺序或在垂直方向上布置。

34. 发明授权

US07229860B2 Method for manufacturing a thin film transistor using poly silicon 有权
标题翻译：使用多晶硅制造薄膜晶体管的方法
公开(公告)号：US07229860B2
公开(公告)日：2007-06-12
申请号：US10499090
申请日：2002-01-29
申请人： Jean-Ho Song , Joon-Hoo Choi , Beom-Rak Choi , Myung-Koo Kang , Sook-Young Kang
发明人： Jean-Ho Song , Joon-Hoo Choi , Beom-Rak Choi , Myung-Koo Kang , Sook-Young Kang
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/78675
摘要： A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl2, SF6 and Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer. A source region and a drain region opposite each other with respect to the gate electrode are formed by implanting impurities into the semiconductor layer and a source electrode and drain electrode are formed to be electrically connected to the source region and drain region.
摘要翻译：薄膜晶体管的制造方法。在绝缘基板上形成非晶硅薄膜，并通过横向固化工艺使激光束照射到非晶硅薄膜中而形成多晶硅薄膜而结晶。接下来，通过使用包含Cl 2，SF 6和Ar的气体混合物的等离子体干蚀刻来除去从多晶硅薄膜的表面突出的突出部分， 3：1：2以平滑多晶硅薄膜的表面，并且通过图案化多晶硅薄膜形成半导体层。形成覆盖半导体层的栅极绝缘膜，并且在与半导体层相对的栅极绝缘膜上形成栅电极。通过将杂质注入到半导体层中而形成源极区和相对于栅极彼此相对的漏极区，源电极和漏电极形成为与源区和漏区电连接。

35. 发明申请

US20070026549A1 Array substrate, method of manufacturing the same and method of crystallizing silicon 有权
标题翻译：阵列基板，其制造方法和硅结晶方法
公开(公告)号：US20070026549A1
公开(公告)日：2007-02-01
申请号：US11386630
申请日：2006-03-22
申请人： Soong-Yong Joo , Myung-Koo Kang
发明人： Soong-Yong Joo , Myung-Koo Kang
IPC分类号： H01L21/00
CPC分类号： H01L27/1285 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/0268 , H01L21/02691 , H01L27/1296 , H01L29/04 , H01L29/66757
摘要： An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.
摘要翻译：阵列基板包括基底基板，开关元件和像素电极。开关元件在基底基板上。开关元件包括具有至少一个块的多晶硅图案。在沿多个方向延伸的至少一个块中的每一个中形成谷粒。像素电极电连接到开关元件。因此，提高了开关元件的电流移动性和设计余量。

36. 发明申请

US20050130357A1 Method for manufacturing a thin film transistor using poly silicon 有权
标题翻译：使用多晶硅制造薄膜晶体管的方法
公开(公告)号：US20050130357A1
公开(公告)日：2005-06-16
申请号：US10499090
申请日：2002-01-29
申请人： Jean-Ho Song , Joon-Hoo Choi , Beom-Rak Choi , Myung-Koo Kang , Sook-Young Kang
发明人： Jean-Ho Song , Joon-Hoo Choi , Beom-Rak Choi , Myung-Koo Kang , Sook-Young Kang
IPC分类号： G02F1/1368 , H01L21/20 , H01L21/208 , H01L21/3065 , H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78675
摘要： A manufacturing method of a thin film transistor. An amorphous silicon thin film is formed on an insulating substrate, and is crystallized by a lateral solidification process with illumination of laser beams into the amorphous silicon thin film to form a polysilicon thin film. Next, protrusion portions protruding from the surface of the polysilicon thin film are removed by plasma dry-etching using a gas mixture including Cl2, SF6 and Ar at the ratio of 3:1:2 to smooth the surface of the polysilicon thin film, and the semiconductor layer is formed by patterning the polysilicon thin film. A gate insulating film covering the semiconductor layer is formed and a gate electrode is formed on the gate insulating film opposite the semiconductor layer. A source region and a drain region opposite each other with respect to the gate electrode are formed by implanting impurities into I the semiconductor layer and a source electrode and drain electrode are forined to be electrically connected to the source region and drain region.
摘要翻译：薄膜晶体管的制造方法。在绝缘基板上形成非晶硅薄膜，并通过横向固化工艺使激光束照射到非晶硅薄膜中而形成多晶硅薄膜而结晶。接下来，通过使用包含Cl 2，SF 6和Ar的气体混合物的等离子体干蚀刻来除去从多晶硅薄膜的表面突出的突出部分， 3：1：2以平滑多晶硅薄膜的表面，并且通过图案化多晶硅薄膜形成半导体层。形成覆盖半导体层的栅极绝缘膜，并且在与半导体层相对的栅极绝缘膜上形成栅电极。通过将杂质注入到半导体层中而形成源极区域和相对于栅极电极相对的漏极区域，源极和漏极电极被电连接到源极区域和漏极区域。

37. 发明申请

US20060176263A1 Display device and method of driving the same 审中-公开
标题翻译：显示装置及其驱动方法
公开(公告)号：US20060176263A1
公开(公告)日：2006-08-10
申请号：US11256449
申请日：2005-10-20
申请人： Myung-Koo Kang , Lintao Zhang , Jung-Sun Lee , Jong-Hwa Park
发明人： Myung-Koo Kang , Lintao Zhang , Jung-Sun Lee , Jong-Hwa Park
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3685 , G09G2300/0408 , G09G2330/026 , G09G2330/12
摘要： A display device includes a data driver, an inverter, a display panel, and an intercept unit. The data driver provides an image signal and the scan driver generates a control signal corresponding to the image signal. The inverter provides an inverted control signal. The display panel has a PMOS transistor that provides the image signal to a pixel electrode based on the inverted control signal. The interception unit intercepts an abnormal signal that is forwarded to the PMOS transistor. Therefore, a signal having an abnormal voltage level may be interrupted to prevent display defects resulting from the abnormal voltage level.
摘要翻译：显示装置包括数据驱动器，逆变器，显示面板和截距单元。数据驱动器提供图像信号，扫描驱动器产生对应于图像信号的控制信号。逆变器提供反相控制信号。显示面板具有PMOS晶体管，其基于反相控制信号将图像信号提供给像素电极。拦截单元拦截转发到PMOS晶体管的异常信号。因此，可能中断具有异常电压电平的信号，以防止由异常电压电平引起的显示缺陷。

38. 发明授权

US08119546B2 Array substrate, method of manufacturing the same and method of crystallizing silicon 有权
标题翻译：阵列基板，其制造方法和硅结晶方法
公开(公告)号：US08119546B2
公开(公告)日：2012-02-21
申请号：US12110678
申请日：2008-04-28
申请人： Soong-Yong Joo , Myung-Koo Kang
发明人： Soong-Yong Joo , Myung-Koo Kang
IPC分类号： C30B1/08 , C30B13/22 , C30B21/04
CPC分类号： H01L27/1285 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/0268 , H01L21/02691 , H01L27/1296 , H01L29/04 , H01L29/66757
摘要： An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.
摘要翻译：阵列基板包括基底基板，开关元件和像素电极。开关元件在基底基板上。开关元件包括具有至少一个块的多晶硅图案。在沿多个方向延伸的至少一个块中的每一个中形成谷粒。像素电极电连接到开关元件。因此，提高了开关元件的电流移动性和设计余量。

39. 发明授权

US08085232B2 Array substrate receiving two polarities opposite to each other and a display device having the same 有权
标题翻译：具有彼此相反的两个极性的阵列基板和具有该极性的显示装置
公开(公告)号：US08085232B2
公开(公告)日：2011-12-27
申请号：US11454651
申请日：2006-06-16
申请人： Soong-Yong Joo , Myung-Koo Kang , Lintao Zhang , Jung-Sun Lee , Suk-Ki Jung , Dong-Yub Lee , Jong-Hwa Park
发明人： Soong-Yong Joo , Myung-Koo Kang , Lintao Zhang , Jung-Sun Lee , Suk-Ki Jung , Dong-Yub Lee , Jong-Hwa Park
IPC分类号： G09G3/36
CPC分类号： G02F1/134336 , G02F1/136286 , G02F2201/40 , G09G3/3614 , G09G3/3677
摘要： An array substrate includes a base substrate, a plurality of gate lines, a plurality of data lines and a pixel matrix. The plurality of gate lines and the plurality of data lines define pixel areas. The pixel matrix is formed on each pixel area, and includes a plurality of pixel columns and pixel rows. Each pixel column has a first pixel group and a second pixel group. The first pixel group is electrically connected to a first gate line adjacent to the pixel column. The second pixel group is electrically connected to a second gate line adjacent to the pixel column. Each pixel row is electrically connected to one data line adjacent to the pixel column.
摘要翻译：阵列基板包括基底基板，多条栅极线，多条数据线和像素矩阵。多个栅极线和多个数据线限定像素区域。像素矩阵形成在每个像素区域上，并且包括多个像素列和像素行。每个像素列具有第一像素组和第二像素组。第一像素组电连接到与像素列相邻的第一栅极线。第二像素组电连接到与像素列相邻的第二栅极线。每个像素行电连接到与像素列相邻的一个数据线。

40. 发明授权

US07405464B2 Array substrate, method of manufacturing the same and method of crystallizing silicon 有权
标题翻译：阵列基板，其制造方法和硅结晶方法
公开(公告)号：US07405464B2
公开(公告)日：2008-07-29
申请号：US11386630
申请日：2006-03-22
申请人： Soong-Yong Joo , Myung-Koo Kang
发明人： Soong-Yong Joo , Myung-Koo Kang
IPC分类号： H01L29/00
CPC分类号： H01L27/1285 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/0268 , H01L21/02691 , H01L27/1296 , H01L29/04 , H01L29/66757
摘要： An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.
摘要翻译：阵列基板包括基底基板，开关元件和像素电极。开关元件在基底基板上。开关元件包括具有至少一个块的多晶硅图案。在沿多个方向延伸的至少一个块中的每一个中形成谷粒。像素电极电连接到开关元件。因此，提高了开关元件的电流移动性和设计余量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式