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31. 发明申请

US20060163558A1 MOS transistor with elevated source/drain structure 有权
标题翻译：具有升高的源极/漏极结构的MOS晶体管
公开(公告)号：US20060163558A1
公开(公告)日：2006-07-27
申请号：US11388868
申请日：2006-03-24
申请人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
发明人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
IPC分类号： H01L31/109
CPC分类号： H01L29/7834 , H01L29/42376 , H01L29/66477 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
摘要翻译：在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是在形成外延层之后形成，从而防止源极/漏极结区域的劣化。此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

32. 发明授权

US07863142B2 Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device 有权
公开(公告)号：US07863142B2
公开(公告)日：2011-01-04
申请号：US12078750
申请日：2008-04-04
申请人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
发明人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

33. 发明申请

US20100233864A1 Methods of fabricating a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100233864A1
公开(公告)日：2010-09-16
申请号：US12656842
申请日：2010-02-17
申请人： Ho Lee , Moon-han Park , Hwa-sung Rhee , Myung-sun Kim , Hoi-sung Chung
发明人： Ho Lee , Moon-han Park , Hwa-sung Rhee , Myung-sun Kim , Hoi-sung Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/2236 , H01L21/265 , H01L21/76825 , H01L21/76829 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在衬底上形成栅极堆叠，在衬底上形成绝缘层以覆盖栅极堆叠，通过蚀刻绝缘层在栅极堆叠的两个侧壁处形成间隔物，以及在间隔物或绝缘层中离子注入杂质。

34. 发明授权

US07619285B2 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 失效
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US07619285B2
公开(公告)日：2009-11-17
申请号：US12029884
申请日：2008-02-12
申请人： Dong-suk Shin , Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Tetsuji Ueno , Ho Lee , Seung-hwan Lee
IPC分类号： H01L29/772 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： A CMOS transistor includes first and second conductivity type MOS transistors. The first conductivity type MOS transistor includes elevated source and drain regions which abut a channel region in a semiconductor substrate and which are formed by elevated epitaxial layers, each including a first epitaxial layer formed in a first recessed of the semiconductor substrate and a second epitaxial layer formed on the first epitaxial layer and extending to a level that is above an upper surface of the semiconductor substrate. The second conductivity type MOS transistor includes recessed source and drain regions which abut a channel region of the semiconductor substrate and which are formed by recessed epitaxial layers, each including a first epitaxial layer formed in a second recess of the semiconductor substrate and a second epitaxial layer formed in the second recess on the first epitaxial layer.
摘要翻译： CMOS晶体管包括第一和第二导电类型的MOS晶体管。第一导电型MOS晶体管包括升高的源极和漏极区域，其邻接半导体衬底中的沟道区域并且由升高的外延层形成，每个包括形成在半导体衬底的第一凹部中的第一外延层和第二外延层形成在所述第一外延层上并延伸到所述半导体衬底的上表面之上的水平。第二导电型MOS晶体管包括凹陷的源极和漏极区域，其邻接半导体衬底的沟道区域并且由凹陷的外延层形成，每个包括形成在半导体衬底的第二凹槽中的第一外延层和第二外延层形成在第一外延层上的第二凹槽中。

35. 发明授权

US07365010B2 Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same 有权
标题翻译：具有含碳金属硅化物层的半导体器件及其制造方法
公开(公告)号：US07365010B2
公开(公告)日：2008-04-29
申请号：US11295784
申请日：2005-12-07
申请人： Hwa-sung Rhee , Hion-suck Baik , Dong-suk Shin , Tetsuji Ueno , Seung-hwan Lee , Ho Lee
发明人： Hwa-sung Rhee , Hion-suck Baik , Dong-suk Shin , Tetsuji Ueno , Seung-hwan Lee , Ho Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/66507 , H01L29/66628
摘要： Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a first metal silicide layer on an upper part thereof which contains carbon and the source/drain regions have second metal silicide layers on their substantially carbon-free upper parts.
摘要翻译：提供了制造具有含碳金属硅化物层的半导体器件的方法和通过该方法制造的半导体器件。代表性的方法包括以下步骤：制备半导体衬底并在半导体衬底上形成栅电极和源极/漏极区，使得栅电极在其上部具有含有碳的第一金属硅化物层和源极/漏极区域在其基本上无碳的上部上具有第二金属硅化物层。

36. 发明申请

US20070023847A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070023847A1
公开(公告)日：2007-02-01
申请号：US11492939
申请日：2006-07-26
申请人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee
发明人： Hwa-sung Rhee , Tetsuji Ueno , Ho Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be formed on the semiconductor substrate. The first spacer may be formed on sidewalls of the gate electrode. The second spacer may be formed on sidewalls of the first spacer. The epitaxial pattern may be formed between the second spacer and the semiconductor substrate such that an outside profile of the epitaxial pattern is aligned with an outside profile of the second spacer. The source/drain regions may include primary source/drain regions that are aligned with the first spacer. The primary source/drain regions may be formed in the epitaxial pattern and the semiconductor substrate. The source/drain regions may also include secondary source/drain regions that are aligned with the second spacer and formed in the semiconductor substrate.
摘要翻译：提供一种制造半导体器件的半导体器件和方法。半导体器件可以包括半导体衬底，栅极绝缘层和栅电极，第一间隔物，第二间隔物，外延图案和/或源极/漏极区域。栅极绝缘层和栅电极可以形成在半导体衬底上。第一间隔物可以形成在栅电极的侧壁上。第二间隔件可以形成在第一间隔件的侧壁上。外延图案可以形成在第二间隔物和半导体衬底之间，使得外延图案的外部轮廓与第二间隔物的外部轮廓对准。源极/漏极区域可以包括与第一间隔物对准的主要源极/漏极区域。初级源极/漏极区域可以形成为外延图案和半导体衬底。源极/漏极区域还可以包括与第二间隔物对准并形成在半导体衬底中的次级源极/漏极区域。

37. 发明申请

US20060121660A1 Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same 有权
标题翻译：具有含碳金属硅化物层的半导体器件及其制造方法
公开(公告)号：US20060121660A1
公开(公告)日：2006-06-08
申请号：US11295784
申请日：2005-12-07
申请人： Hwa-sung Rhee , Hion-suck Baik , Dong-suk Shin , Tetsuji Ueno , Seung-hwan Lee , Ho Lee
发明人： Hwa-sung Rhee , Hion-suck Baik , Dong-suk Shin , Tetsuji Ueno , Seung-hwan Lee , Ho Lee
IPC分类号： H01L21/8234 , H01L21/4763
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/66507 , H01L29/66628
摘要： Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a first metal silicide layer on an upper part thereof which contains carbon and the source/drain regions have second metal silicide layers on their substantially carbon-free upper parts.
摘要翻译：提供了制造具有含碳金属硅化物层的半导体器件的方法和通过该方法制造的半导体器件。代表性的方法包括以下步骤：制备半导体衬底并在半导体衬底上形成栅电极和源极/漏极区，使得栅电极在其上部具有含有碳的第一金属硅化物层和源极/漏极区域在其基本上无碳的上部上具有第二金属硅化物层。

38. 发明授权

US07033895B2 Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process 有权
标题翻译：使用选择性外延生长工艺制造具有升高的源极/漏极结构的MOS晶体管的方法
公开(公告)号：US07033895B2
公开(公告)日：2006-04-25
申请号：US10823420
申请日：2004-04-13
申请人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
发明人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/42376 , H01L29/66477 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
摘要翻译：在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是在形成外延层之后形成，从而防止源极/漏极结区域的劣化。此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

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