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31. 发明授权

US09030976B2 Bi-directional digital interface for video and audio (DIVA) 有权
标题翻译：视频和音频双向数字接口（DIVA）
公开(公告)号：US09030976B2
公开(公告)日：2015-05-12
申请号：US12057051
申请日：2008-03-27
申请人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
发明人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
IPC分类号： H04B1/52 , H04N5/44 , H04N5/765 , H04N5/85 , H04N21/43 , H04N21/4363
CPC分类号： H04N5/44 , H04N5/765 , H04N5/85 , H04N21/4305 , H04N21/43632 , H04N21/43635
摘要： A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.
摘要翻译：一种通信系统，包括第一节点，第二节点，第一节点和第二节点之间的串行通信链路，用于经由链路的一个或多个视频信道从第一节点向第二节点发送数字视频数据。所述通信系统还包括在所述第一节点和所述第二节点之间的混合链路，其中所述第一节点和所述第二节点被配置为通过所述混合链路通过混合信道将至少一个数据流发送到另一个。在通信系统中，根据视频像素频率对串行通信链路的带宽进行缩放。此外，串行通信链路的初始锁定由通过混合链路传送的时钟信息辅助。

32. 发明授权

US08908576B2 Bi-directional digital interface for video and audio (DIVA) 有权
公开(公告)号：US08908576B2
公开(公告)日：2014-12-09
申请号：US12057051
申请日：2008-03-27
申请人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
发明人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
IPC分类号： H04B1/52 , H04N5/44 , H04N21/43 , H04N5/765 , H04N5/85 , H04N21/4363
摘要： A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

33. 发明授权

US08160192B2 Signal interleaving for serial clock and data recovery 有权
标题翻译：信号交错用于串行时钟和数据恢复
公开(公告)号：US08160192B2
公开(公告)日：2012-04-17
申请号：US11861175
申请日：2007-09-25
申请人： Dongyun Lee , Sungjoon Kim
发明人： Dongyun Lee , Sungjoon Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812
摘要： A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.
摘要翻译：一种用于从串行数据流中恢复定时信息和数据的时钟和数据恢复（CDR）系统和方法。 CDR系统包括产生恢复的时钟/数据信号的采样电路和向采样电路提供反馈的交错反馈网络。反馈网络包括基于恢复的时钟/数据信号产生控制信号的逻辑电路，第一多路复用器，其基于控制信号从全局时钟信号的四相中选择第一延迟锁定环，第一延迟锁定环具有第一组延迟单元，耦合到第二多路复用器，其基于所选择的全局时钟信号产生延迟的信号;以及第二延迟锁定环，其具有产生一组相移反馈信号的第二组延迟单元，所述相移反馈信号被施加到采样电路使采样电路与接收到的串行数据流中的转换相对齐。

34. 发明授权

US07949863B2 Inter-port communication in a multi-port memory device 有权
标题翻译：多端口存储设备中的端口间通信
公开(公告)号：US07949863B2
公开(公告)日：2011-05-24
申请号：US11694819
申请日：2007-03-30
申请人： Alan T. Ruberg , Dae Kyeung Kim , Daeyun Shim , Dongyun Lee , Myung Rai Cho , Sungjoon Kim
发明人： Alan T. Ruberg , Dae Kyeung Kim , Daeyun Shim , Dongyun Lee , Myung Rai Cho , Sungjoon Kim
IPC分类号： G06F9/48 , G06F15/76
CPC分类号： G11C8/16 , G06F13/4054 , G06F13/4243 , G11C7/1075 , G11C2207/108
摘要： A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
摘要翻译：一种利用多端口存储器件进行端口间通信的方法和系统。存储器件包含中断寄存器，中断信号接口（例如，专用引脚），中断掩码以及与每个端口相关联的一个或多个消息缓冲器。当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时，第一组件将消息写入与第二端口相关联的消息缓冲器。第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。在接收到中断时，第二个组件读取中断寄存器以确定中断的性质。然后第二个组件从消息缓冲区读取消息。

35. 发明申请

US20080235526A1 POWER-SAVING CLOCKING TECHNIQUE 有权
标题翻译：省电时钟技术
公开(公告)号：US20080235526A1
公开(公告)日：2008-09-25
申请号：US11690659
申请日：2007-03-23
申请人： Dongyun Lee
发明人： Dongyun Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3215 , Y02D10/126 , Y02D50/20
摘要： A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.
摘要翻译：提供了一种称为混合时钟系统的用于提供具有降低的功耗的时钟信号的方法和系统。混合时钟系统使用PLL进行高速数据传输，但提供了一种省电模式，用于传输数据，同时消耗较少的功耗。在正常模式下，混合时钟系统包含以驱动PLL的低频工作的参考时钟。 PLL将参考时钟频率乘以高得多的频率，并将时钟信号提供给数据传输电路。在省电模式下，混合时钟系统关闭PLL并将参考时钟直接连接到数据传输电路。

36. 发明申请

US20080126824A1 COMMUNICATIONS ARCHITECTURE FOR MEMORY-BASED DEVICES 有权
标题翻译：基于存储器件的通信架构
公开(公告)号：US20080126824A1
公开(公告)日：2008-05-29
申请号：US11828286
申请日：2007-07-25
申请人： Dongyun Lee , Yeshik Shin , David D. Lee , Deog-Kyoon Jeong , Shing Kong
发明人： Dongyun Lee , Yeshik Shin , David D. Lee , Deog-Kyoon Jeong , Shing Kong
IPC分类号： G06F1/08 , G06F12/02
CPC分类号： H04L47/10 , H04L47/245 , H04L47/34 , H04L47/365
摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
摘要翻译：用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的。存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

37. 发明申请

US20070201546A1 Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer 有权
标题翻译：具有可控加权的并行高通和低通滤波器的均衡器和包括这种均衡器的接收器
公开(公告)号：US20070201546A1
公开(公告)日：2007-08-30
申请号：US11796175
申请日：2007-04-27
申请人： Dongyun Lee
发明人： Dongyun Lee
IPC分类号： H03H7/30 , H04B1/10
CPC分类号： H04L25/03159 , H04L63/04 , H04L63/166 , H04L2025/03356 , H04L2025/03522
摘要： An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (β), and a second branch including a high pass filter (HPF) and having another variable gain (α). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters β and α are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver. In some embodiments useful for equalizing a differential input signal, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. The current sources are independently controllable. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0.(β+α·(1+s·C0·Z0)), where β is a gain parameter determined by the tail current of one differential pair and α is a gain parameter determined by the tail current of the other differential pair.
摘要翻译：一种可调均衡器，包括包括低通滤波器（LPF）并且具有可变增益（β）的第一分支，以及包括高通滤波器（HPF）并具有另一可变增益（α）的第二分支）。响应于输入信号的分支的输出被相加以产生均衡的输出。均衡器可以使用CMOS技术来实现，使得增益参数β和α可独立调节，并且均衡器能够均衡指示具有至少1Gb / s的最大数据速率的数据的输入。通常，本发明的均衡器被实现在接收机中，用于均衡通过串行链路传播到接收机的视频或其他数据的信号。在用于均衡差分输入信号的一些实施例中，均衡器包括两个MOS晶体管的差分对，并且可控电流源确定每个差分对的尾部电流。目前的来源是独立可控的。当均衡器包括纯电阻阻抗Z0和Z1时，均衡器的传递函数为Z1 / Z0（β+α（1 + s.C0.Z0）），其中β是由一个差分的尾电流确定的增益参数 pair和alpha是由另一个差分对的尾部电流确定的增益参数。

38. 发明授权

US08680712B2 Power delivery over digital interaction interface for video and audio (DiiVA) 有权
标题翻译：视频和音频数字交互接口（DiiVA）
公开(公告)号：US08680712B2
公开(公告)日：2014-03-25
申请号：US12636063
申请日：2009-12-11
申请人： Dongyun Lee , Edward Pak , John Hahn , Mayank Gupta
发明人： Dongyun Lee , Edward Pak , John Hahn , Mayank Gupta
IPC分类号： H02J1/00 , G06F3/00
CPC分类号： H02J3/02 , G06F13/14 , H04L12/10 , H04L12/40045 , H04L2012/2849 , H04N5/63 , H04N7/108 , H04N21/436 , Y10T307/492 , Y10T307/56
摘要： A system for delivering power over a network of devices connected through a serial link includes a first and second differential pairs of wires. Each differential pair of wires is double AC coupled by a HPF on one side and by another HPF on an opposite side. An LPF connects a portion of each differential pair of wires between the HPFs to a voltage source, and another LPF connects that portion of each differential pair to a load. The system further includes a third and fourth differential pairs of wires. All four differential pairs of wires are located within a single cable, such as a CAT6 cable. The first, second and third differential pair of wires are used for video links, and the fourth differential pair of wires are used for the bi-directional hybrid link. A power delivery circuit in each device includes a voltage source, a power relay switch, a signature resistor for detection, and a load detector.
摘要翻译：用于通过串联链路连接的设备的网络上传送电力的系统包括第一和第二差分线对。每条差分对导线在一侧由HPF双相交流耦合，另一侧的另一HPF耦合。 LPF将HPF之间的每对差分对导线的一部分连接到电压源，另一个LPF将每个差分对的该部分连接到负载。该系统还包括第三和第四差动对的导线。所有四条差分对的导线位于单根电缆内，如CAT6电缆。第一，第二和第三差分线对用于视频链路，并且第四差分对导线用于双向混合链路。每个装置中的电力输送电路包括电压源，功率继电器开关，用于检测的签名电阻器和负载检测器。

39. 发明申请

US20130191570A1 MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA) 审中-公开
标题翻译：多媒体用于视频和音频的数字交互界面的USB数据传输（DiiVA）
公开(公告)号：US20130191570A1
公开(公告)日：2013-07-25
申请号：US13521739
申请日：2011-01-12
申请人： Dongyun Lee , Edward Pak , John Hahn , Mayank Gupta , Byoung Woon Kim , Paul Heninwolf , Sangwan Kim , Sukjae Cho
发明人： Dongyun Lee , Edward Pak , John Hahn , Mayank Gupta , Byoung Woon Kim , Paul Heninwolf , Sangwan Kim , Sukjae Cho
IPC分类号： G06F13/42
CPC分类号： H04N21/43615 , G06F13/4286 , G09G2370/047 , G09G2370/12 , H04L12/2838 , H04L2012/2849 , H04N21/43632 , H04N21/43635 , H04N21/63
摘要： A system for delivering USB data over a DiiVA network may include a USB host controller, at least one USB device, a first DiiVA device connected to the USB host controller through an upstream USB port, a second DiiVA device connected to the USB device through a downstream USB port; and a network configured to transfer data between the first DiiVA device and the second DiiVA device according to USB protocol through a DiiVA bi-directional hybrid link in the network. The network is responsive to the USB host controller to deliver contents for the USB protocol through at least one line state information packet and at least one USB data packet transmitted through the hybrid link between the upstream USB port and the downstream USB port.
摘要翻译：用于通过DiiVA网络传送USB数据的系统可以包括USB主机控制器，至少一个USB设备，通过上游USB端口连接到USB主机控制器的第一DiiVA设备，通过一个USB设备连接到USB设备的第二个DiiVA设备下游USB端口; 以及网络，被配置为通过网络中的DiiVA双向混合链路，根据USB协议在第一DiiVA设备和第二DiiVA设备之间传送数据。网络响应于USB主机控制器，通过至少一个线路状态信息包和通过上游USB端口和下游USB端口之间的混合链路传输的至少一个USB数据包来传送用于USB协议的内容。

40. 发明申请

US20120314753A1 Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer 审中-公开
标题翻译：均衡器具有可控加权平行高通和低通滤波器和接收器，包括这样的均衡器
公开(公告)号：US20120314753A1
公开(公告)日：2012-12-13
申请号：US13592630
申请日：2012-08-23
申请人： Dongyun Lee
发明人： Dongyun Lee
IPC分类号： H04L27/01
CPC分类号： H04L25/03159 , H04L63/04 , H04L63/166 , H04L2025/03356 , H04L2025/03522
摘要： An adjustable equalizer that includes a first branch including a low pass filter (LPF) typically having a variable gain (β), and a second branch including a high pass filter (HPF) typically having another variable gain (α). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology and can be capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.
摘要翻译：一种包括通常具有可变增益的低通滤波器（LPF）的第一分支的可调平衡器，以及包括通常具有另一可变增益（α）的高通滤波器（HPF）的第二分支。响应于输入信号的分支的输出被相加以产生均衡的输出。均衡器可以使用CMOS技术来实现，并且能够使指示具有至少1Gb / s的最大数据速率的数据的输入均衡。通常，均衡器被实现在接收机中，用于均衡通过串行链路传播到接收机的信号，指示视频或其他数据。

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