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31. 发明专利

JPH07321247A BGA TYPE SEMICONDUCTOR DEVICE AND BOARD FOR MOUNTING THE SAME 失效
公开(公告)号：JPH07321247A
公开(公告)日：1995-12-08
申请号：JP11250194
申请日：1994-05-26
申请人： HITACHI LTD
发明人： KONO RYUJI , KUMAZAWA TETSUO , KITANO MAKOTO , YAGUCHI AKIHIRO , YONEDA NAE , TANAKA TADAYOSHI
IPC分类号： H05K1/18 , H01L21/60 , H01L23/12 , H05K1/11 , H05K3/34
摘要： PURPOSE:To lengthen the life time of a solder which is associated with a thermal distortion, by making the value of its angle of contact in the generative direction of the thermal distortion larger than the ones present in conventional mounting states. CONSTITUTION:The shape of a pad 14 of a BGA is so set that its dimension in the direction of the segment which passes both deformation center 12 and it is made larger than the one in the orthogonal direction thereto. Also, each pad of a board has a substantially the same shape as the pad 14 soldered thereto. The deformation center 12 is made present in the predetermined position forcedly. Thereby, the angle whereat a solder ball is contacted with the BGA or the board is made larger than conventional ones. Since the deformation center 12 can be determined definitely, the shape and direction of the pad 14 are made optimum respectively, and the life time of the solder can be made long.

32. 发明专利

JPH0786335A SEMICONDUCTOR MOUNTING STRUCTURE AND RESIN-SEALED SEMICONCUCTOR DEVICE USED THEREIN 失效
公开(公告)号：JPH0786335A
公开(公告)日：1995-03-31
申请号：JP23279293
申请日：1993-09-20
申请人： HITACHI LTD
发明人： TANAKA TADAYOSHI , KUMAZAWA TETSUO , NISHIMURA ASAO , YAGUCHI AKIHIRO , KONO RYUJI , SHIMIZU HIROYA , ANJO ICHIRO
IPC分类号： H01L21/56 , H01L21/60 , H01L23/12 , H01L23/28 , H01L23/50 , H05K3/34
摘要： PURPOSE:To make it possible to ready for a multipin structure, to prevent the generation of defective connection between a solder bump and the outer wiring due to warpage, and to improve heat radiating property. CONSTITUTION:The back side of the chip-mounted surface of a wiring substrate 2 is connected to an outer wiring substrate 10 through the intermediary of a solder bump 4. Also, a plurality of leads 3 are arranged at least on one of the side faces of a semiconductor chip 1 in four directions, and the semiconductor chip 1 and the leads 3 are electrically connected. As the solder bump 4 and the leads 3 are mounted on the outer wiring board 10 as above-mentioned, a multipin construction can be formed, the pitch of the solder bump can be widely set without decreasing the number of pins, and the connection reliability when mounting can be improved. Also, by the interposition of the lead between the wiring substrate 2 and sealing resin 5, the warpage generated by molding can be alleviated and the reliability can be improved by the lowering of stress.

33. 发明专利

JPH0750388A RESIN-SEALED SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0750388A
公开(公告)日：1995-02-21
申请号：JP19624293
申请日：1993-08-06
申请人： HITACHI LTD
发明人： YAGUCHI AKIHIRO , NISHIMURA ASAO , KONO RYUJI , TANAKA TADAYOSHI
IPC分类号： H01L25/10 , H01L25/18
摘要： PURPOSE:To enable a resin-sealed semiconductor device high in packaging density to be enhanced in productivity by a method wherein outer leads are composed of one outer lead bonded to a board and another outer lead used for connecting the adjacent resin-sealed semiconductor devices together. CONSTITUTION:Semiconductor elements 1 and 11 are bonded to chip pads 2 and 22 respectively for fixing. Leads around the semiconductor elements 1 and 11 are electrically connected to the semiconductor elements 1 and 11 with metal fine wires 4. A linking lead 3a out of the leads is so connected that the semiconductor elements 1 and 11 may have a continuity together inside packages 6 and 66. Outer connection leads 3b and 33b are connected to a board outside the packages 6 and 66. The linking lead 3a is led out of the sides of the packages 6 and 66 opposite to the other sides through which the outer connection leads 3b and 33b are made to protrude.

34. 发明专利

JPH06268145A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06268145A
公开(公告)日：1994-09-22
申请号：JP5161593
申请日：1993-03-12
申请人： HITACHI LTD
发明人： KONO RYUJI , NISHIMURA ASAO , YAGUCHI AKIHIRO , TANAKA TADAYOSHI
IPC分类号： H01L23/28 , H01L23/50
摘要： PURPOSE:To obtain the title semiconductor device wherein it can prevent the production of a reflow crack by a new mechanism caused by the exfoliation of a die bonding layer by a method wherein a protrusion part is cut and raised from the inside of the protruding region of a tab and the protrusion part is covered with a sealing resin up to its tip end. CONSTITUTION:A semiconductor element 2 is mounted on a tab 11 in a led frame, individual electrodes on the surface of the semiconductor element 2 are connected electrically to individual prescribed leads in the lead frame, and they are sealed with a sealing resin. In such a semiconductor device, the tab 11 protrudes to the periphery from a semiconductor-element mounting region, a protrusion part 15 is cut and raised toward the outer part than the surface and/or the rear surface of the tab 11 from the inside of its protruding region, and the protrusion part 15 is covered with the sealing resin up to its tip part 152. For example, a hook lead 15 as shown in the figure is formed in a part at the outer side than the outer shape of a semiconductor element inside a plane on a tab 11, and it is bent toward the upper part.

35. 发明专利

JPH06268101A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE, ELECTRONIC DEVICE, LEAD FRAME, AND MOUNTING SUBSTRATE 失效
公开(公告)号：JPH06268101A
公开(公告)日：1994-09-22
申请号：JP5680593
申请日：1993-03-17
申请人： HITACHI LTD
发明人： KITANO MAKOTO , NISHIMURA ASAO , YAGUCHI AKIHIRO , YONEDA NAE , KONO RYUJI , TANAKA TADAYOSHI , KUMAZAWA TETSUO
IPC分类号： H01L21/56 , H01L23/12 , H01L23/13 , H01L23/28 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L25/11 , H01L25/16 , H01L25/18 , H05K1/18 , H05K3/34
摘要： PURPOSE:To provide a highly reliable structure for multi-pin packages which can be mass-produced at a low cost and its manufacturing method. CONSTITUTION:A pair of holes 7 reaching the upper and lower surfaces of a package is formed at prescribed positions of each inner lead 4 by using a metallic mold having projections on the package forming surfaces of its top and bottom molds and sealing the inner leads with a resin 6 while a lead frame is held between the projections. Since the surface of the lead frame is not coated nor contaminated with the resin 6, solder bumps 5 connected to the lead frame can be arranged two-dimensionally on the surface of the package by using ordinary cream solder. Therefore, a multi-pin package which can be excellently mass-produced can be provided and the mounting density of electronic parts can be increased.

36. 发明专利

JP2002353388A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002353388A
公开(公告)日：2002-12-06
申请号：JP2001162282
申请日：2001-05-30
申请人： HITACHI LTD
发明人： TANAKA TADAYOSHI , NAKAZATO NORIO , KIKUCHI HIROSHI , NOSE FUJIAKI , KUBO TAKASHI , AOKI TETSUYA , YOSHIMOTO KENJI
IPC分类号： H01L23/36 , H01L23/34 , H01L23/367 , H01L23/42 , H01L31/02 , H01L33/64 , H01S5/024 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with excellent radiation and high reliability reducing easing strain by surely embedding a thermal conduction member at low load without producing a gap between an electronic part including a heat generating element and a casing and its manufacturing method. SOLUTION: The semiconductor device having a low load radiation mounting structure is realized for the casings 5, 6 and a semiconductor package 2 even when the compression rate of a thermal conduction rubber sheet 8 is high by utilizing the stress relaxation of the thermal conduction rubber sheet 8 under a low temperature heating environment.

37. 发明专利

JP2002270755A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002270755A
公开(公告)日：2002-09-20
申请号：JP2001064316
申请日：2001-03-08
申请人： HITACHI LTD
发明人： NAKA YASUHIRO , TANAKA TADAYOSHI , YOSHIDA IKUO , IMASU SEISHI , NAITO TAKAHIRO
IPC分类号： H01L25/18 , H01L21/56 , H01L23/28 , H01L25/04 , H01L25/065 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide the MCM-type semiconductor device of reliable structure for suppressing reduction in its soundness, with respect to thermal expansion, etc., to operation. SOLUTION: A multi-chip module type semiconductor device is provided with semiconductor elements, provided with the first bumps which are in electrical contact with a substrate and the substrate mounting the multiple semiconductor elements via the first bumps and having the second bump in electrical contact with a mother board. The thickness of the semiconductor elements is smaller than that of the substrate.

38. 发明专利

JPH11265971A TSOP SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11265971A
公开(公告)日：1999-09-28
申请号：JP6647098
申请日：1998-03-17
申请人： HITACHI LTD
发明人： TANAKA TADAYOSHI , YAGUCHI AKIHIRO , KONO RYUJI , KOJIMA KIYOMI , TERASAKI TAKESHI , MIURA HIDEO , ARITA JUNICHI , IMURA CHIKAKO
IPC分类号： H01L23/50 , H01L23/495
摘要： PROBLEM TO BE SOLVED: To protect a TSOP semiconductor device against package cracks when a lead frame is formed of copper (alloy), by a method wherein a common inner lead is lessened both in width and in thickness. SOLUTION: The width d of a part 1a of a common inner lead 1 arranged in parallel with a direction in which electrodes are disposed in rows is set as wide as 0.2 mm or below. On the cross section A-A' of an inner lead 3 in a TSOP(Thin Small Outline Package) where a copper frame is used, a resin layer on a chip is designed to be 0.37 mm or below in thickness, and the resin layer of a finished product is set as thick as 0.39 mm or below taking irregularities in thickness at molding into consideration so as to protect a package against warpage after the package is sealed up with resin. By this setup, in a TSOP semiconductor device of LOC (Lead On Chip) structure where a copper (alloy) frame is used, the semiconductor device can be improved in reliability due to that stress imposed on a resin part in a thermal cycle test is lessened.

39. 发明专利

JPH11186453A BGA TYPE SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURAL BODY FOR THE DEVICE 失效
公开(公告)号：JPH11186453A
公开(公告)日：1999-07-09
申请号：JP35790997
申请日：1997-12-25
申请人： HITACHI LTD
发明人： HOZOJI HIROYUKI , TSUNODA SHIGEHARU , SAEKI JUNICHI , KANEMITSU NOBUYA , HARUTA AKIRA , SATO TOSHIYA , TANAKA TADAYOSHI , NAGAI AKIRA
IPC分类号： H01L21/60 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a BGA type semiconductor device whose mounting on a mounting substrate or whose repair work can be easily attained, and the mounting structural body. SOLUTION: A BGA type semiconductor device is provided with a flexible substrate 2 whose surface is provided with a wiring pattern 10, and whose central part is opened; semiconductor element 6 arranged in an opening 2b of the flexible substrate 2, and whose surface is provided with an electrode 6a connected with a wiring pattern 10; resin 8 for sealing the surface of the semiconductor element 6 and a terminal area with the electrode 6a in the wiring pattern 10; and a metallic board-shaped body 1 with a difference in level corresponding to a difference in height between the back face of the semiconductor element 6 and the back face of the flexible substrate 2, which is provided with a central high plate-shaped part 1a and a surrounding low plate-shaped part 1b bonded with adhesive between each back face, and an opening at the difference in level part for connecting the central high plate-shaped part 1a with the surrounding plate-shaped part 1b or at the neighboring part of the difference in level part.

40. 发明专利

JPH1098073A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JPH1098073A
公开(公告)日：1998-04-14
申请号：JP16619397
申请日：1997-06-23
申请人： HITACHI LTD
发明人： HASHIZUME TAKANORI , TANAKA TADAYOSHI , SAEKI JUNICHI , TOJO SHINJI , HARUTA AKIRA , ANJO ICHIRO , NISHIMURA ASAO , NISHI KUNIHIKO , NAGAI AKIRA
IPC分类号： H01L21/60 , H01L23/12 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit which is not only enhanced in number of pins, lessened in size, weight and thickness but also enhanced in mounting stability by a method, wherein the outer terminals of a semiconductor chip are arranged on the periphery of the semiconductor chip, and bump electrodes are arranged in two rows on the periphery of a region located outside the semiconductor chip. SOLUTION: Bonding pads 7 are arranged as a square along the periphery of a semiconductor chip 1. A flexible board 2 is composed of a tape 8 and a wiring 10, bonded to the tape 8 through the intermediary of adhesive material 9. A solder resist 3 is formed on the main surface of the wiring 10, excluding a part where solder bumps 4 are connected to the bump lands 12 of the wiring 10 through the opening provided to the solder resist 3, so as to protect the exposed part of the wiring 10. The solder bumps 4 are arranged in two rows in an outer region outside the periphery of the semiconductor chip 1, so as to be separated from each other by a distance of 0.5mm. A reinforcing frame 5 is bonded with an adhesive agent 13.

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