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31. 发明授权

US06985007B2 Signal transmitting receiving apparatus 失效
标题翻译：信号发送接收装置
公开(公告)号：US06985007B2
公开(公告)日：2006-01-10
申请号：US10708235
申请日：2004-02-18
申请人： Hiroyuki Yamauchi , Tadahiro Yoshida
发明人： Hiroyuki Yamauchi , Tadahiro Yoshida
IPC分类号： H03K19/003
CPC分类号： H01P5/02
摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
摘要翻译：根据本发明的信号发送/接收装置包括：发送装置，用于发送数据; 用于接收数据的接收装置; 用于发送数据的数据线; 以及用于发送用于确定数据线的电压的偏置电压的电源线，其中所述发送装置和所述接收装置通过所述数据线和所述供给线彼此连接，所述发送装置包括：驱动器电路，用于输出数据到数据线; 以及偏置产生装置，用于产生所述偏置电压并将偏置电压输出到所述电源线，所述接收装置包括：终端电阻，连接到所述数据线; 以及用于检测来自数据线的数据的接收器电路，其中数据线经由终端电阻器连接到电源线。

32. 发明申请

US20050034093A1 Semiconductor integrated circuit device and method for designing the same 有权
标题翻译：半导体集成电路器件及其设计方法
公开(公告)号：US20050034093A1
公开(公告)日：2005-02-10
申请号：US10935094
申请日：2004-09-08
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G06F17/50 , G11C11/412 , H01L21/3205 , H01L21/82 , H01L21/8244 , H01L23/52 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , G06F17/5045 , G06F17/5068 , G06F2217/08 , G11C11/412 , H01L27/1104
摘要： A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.
摘要翻译：半导体集成电路器件具有由形成在衬底上的电路元件或电线组成的多个设计图案。根据每个设计图案的几何特征，多个设计图案的各个成品尺寸具有多个不同于一种设计图案的最小尺寸值。

33. 发明授权

US06826074B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06826074B2
公开(公告)日：2004-11-30
申请号：US10623691
申请日：2003-07-22
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C1100
CPC分类号： G11C7/12
摘要： In a semiconductor memory device, a precharge potential for non-selected bit lines among a plurality of bit lines, supplied by a HPR voltage source, is set at a value (for example, ½ Vcc=0.4 V) lower than the power supply voltage Vcc (low voltage in the range of 0.5 V to 1.2 V; for example, 0.8 V) determining the high-level side potential of data stored in a memory cell. A potential for non-selected word lines among a plurality of word lines, supplied by a NWL voltage source, is set at a predetermined negative potential (for example, −¼ Vcc=−0.2 V). The total of the precharge potential (0.4 V) of non-selected bit lines and the absolute value of the negative potential (−0.2 V) of non-selected word lines is set at a value less than the power supply voltage Vcc (0.8 V). By these settings, gate leakage current and GIDL current can be effectively limited to a small value while realizing effective limitation of OFF leakage current in a plurality of memory cells.
摘要翻译：在半导体存储器件中，由HPR电压源提供的多个位线之中的未选位线的预充电电位被设定为比电源电压低的值（例如，½Vcc = 0.4V） Vcc（在0.5V至1.2V的范围内的低电压，例如0.8V）确定存储在存储单元中的数据的高电平侧电位。由NWL电压源提供的多个字线中的未选字线的电位被设定为预定的负电位（例如，-¼Vcc = -0.2V）。非选择位线的预充电电位（0.4V）和非选择字线的负电位（-0.2V）的绝对值的总和被设定为小于电源电压Vcc（0.8V ）。通过这些设定，能够有效地将栅泄漏电流和GIDL电流限制在小的值，同时实现多个存储单元中的OFF漏电流的有效限制。

34. 发明授权

US06770940B2 Semiconductor integrated circuit and method for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06770940B2
公开(公告)日：2004-08-03
申请号：US10445807
申请日：2003-05-28
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H01L2976
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.
摘要翻译：在一个芯片上形成第一到第三逻辑电路和第一至第三静态随机存取存储器（SRAM）。对第一和第三逻辑电路及其SRAM的电源根据需要关闭，同时保持供给第二逻辑电路及其SRAM的电源。第三个SRAM具有最大的存储容量。将第一至第三SRAM单元阵列的平均通道宽度设置为其他电路块的平均通道宽度的一半或更小，并且将以低速工作的第二和第三SRAM单元阵列的沟道杂质浓度设置得更高比通过额外的离子注入高速运行的第一个SRAM单元阵列的SRAM单元阵列。通过这些设置，为第一SRAM单元阵列提供低阈值电压（Vt）的MOS晶体管，而为第二和第三SRAM单元阵列提供高Vt的MOS晶体管用于泄漏减少。

35. 发明授权

US06750555B2 Semiconductor SRAM having linear diffusion regions 有权
标题翻译：具有线性扩散区域的半导体SRAM
公开(公告)号：US06750555B2
公开(公告)日：2004-06-15
申请号：US10263914
申请日：2002-10-03
申请人： Katsuji Satomi , Hiroyuki Yamauchi
发明人： Katsuji Satomi , Hiroyuki Yamauchi
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.
摘要翻译：半导体存储器件具有SRAM存储单元，其包括：第一反相器，包括第一nMOS晶体管和第一pMOS晶体管; 包括第二nMOS晶体管和第二pMOS晶体管的第二反相器; 第三个nMOS晶体管; 以及第四nMOS晶体管，其中分别形成所述第一和第三nMOS晶体管的第一扩散区域和形成所述第二和第四nMOS晶体管的第二扩散区域被布置成线形，而没有任何弯曲部分，并且所述第一扩散区域的驱动能力并且第二nMOS晶体管高于第三和第四nMOS晶体管的晶体管。

36. 发明授权

US06246724B1 Signal transfer method 失效
标题翻译：信号传输方式
公开(公告)号：US06246724B1
公开(公告)日：2001-06-12
申请号：US09533982
申请日：2000-03-23
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H04L2534
CPC分类号： H04L5/20 , H04L25/49
摘要： A signal transfer method for transferring a multi-bit signal over a transfer path which is allocated to one bit includes the steps of: respectively assigning a plurality of parameters for a plurality of bits so that a value representing “0” or a value representing “1” is set to each of the plurality of parameters in accordance with a value of a corresponding one of the plurality of bits; outputting an electric signal to the transfer path, the electric signal expressing a combination of the plurality of parameters having the values as set in the assigning step; receiving the electric signal from the transfer path and extracting the plurality of parameters from the electric signal; and detecting the respective values of the plurality of parameters.
摘要翻译：用于通过分配给一位的传送路径传送多位信号的信号传送方法包括以下步骤：分别分配多个比特的多个参数，使得表示“0”的值或表示“ 1“根据多个比特中的相应一个比特的值被设置为多个参数中的每一个; 向所述传送路径输出电信号，所述电信号表示具有在所述分配步骤中设定的值的所述多个参数的组合; 从传输路径接收电信号并从电信号中提取多个参数; 以及检测所述多个参数的相应值。

37. 发明授权

US6127950A Transmission circuit and reception circuit 失效
标题翻译：传输电路和接收电路
公开(公告)号：US6127950A
公开(公告)日：2000-10-03
申请号：US244764
申请日：1999-02-05
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： Image data is transmitted from a memory to a CPU (central processing unit). A transmission circuit of the memory receives an 8-bit source parallel signal, makes reference to transmission histories or to transmission predictions to generate a 2-bit coded parallel signal from the source parallel signal, and sends a serial signal as a result of converting the coded parallel signal, together with a flag signal indicative of the presence of an encoding. If the source parallel signal remains unchanged, the coded parallel signal is made to indicate 00 so that the bit transition probability of the serial signal is reduced. A reception circuit of the CPU receives the serial and flag signals and restores the 8-bit source parallel signal on the basis of reception histories or on the basis of reception predictions. If the transmission circuit fails in performing an encoding, then a serial signal as a result of directly converting the source parallel signal is sent together with a flag signal indicative of the absence of an encoding.
摘要翻译：图像数据从存储器发送到CPU（中央处理单元）。存储器的发送电路接收8位源并行信号，参照发送历史或发送预测，从源并行信号生成2比特编码并行信号，作为转换结果的结果发送串行信号编码并行信号，以及指示编码存在的标志信号。如果源并行信号保持不变，则将编码的并行信号指示为00，使得串行信号的位转移概率减小。 CPU的接收电路接收串行和标志信号，并根据接收历史或基于接收预测恢复8位源并行信号。如果发送电路执行编码失败，则作为直接转换源并行信号的结果的串行信号与指示不存在编码的标志信号一起发送。

38. 发明授权

US5689469A Semiconductor memory devices 失效
标题翻译：半导体存储器件
公开(公告)号：US5689469A
公开(公告)日：1997-11-18
申请号：US742537
申请日：1996-11-01
申请人： Hideo Asaka , Hiroyuki Yamauchi
发明人： Hideo Asaka , Hiroyuki Yamauchi
IPC分类号： G11C8/08 , G11C11/408 , G11C11/4094 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/4085 , G11C29/02 , G11C29/50 , G11C8/08 , G11C11/401
摘要： Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.
摘要翻译：当没有选择字线（待机）时，预充电电路将多对位线预充电到指定的电位。当对应的字线未被选择时，下拉晶体管导通，以将相应的字线连接到连接到地的公共电源线。在将上述公共电源线连接到地线的路径中设置有阻抗改变装置，用于改变在待机期间的值之间的路径的阻抗和在其中选择任何字线的操作期间的另一个值，使得待机期间的值为设置高于操作期间的值。因此，在待机期间，由位线和字线之间的短路引起的漏电流（待机电流）减小。

39. 发明授权

US5450139A Apparatus for transmitting video signals comprising a memory backup device 失效
标题翻译：用于发送包括存储器备份设备的视频信号的装置
公开(公告)号：US5450139A
公开(公告)日：1995-09-12
申请号：US168230
申请日：1993-12-17
申请人： Hideo Haraguchi , Kaichi Tatsuzawa , Hiroyuki Yamauchi
发明人： Hideo Haraguchi , Kaichi Tatsuzawa , Hiroyuki Yamauchi
IPC分类号： H04N5/268 , H04N5/222
CPC分类号： H04N5/222 , H04H60/06 , H04H60/27
摘要： Apparatus for transmitting video signals includes a primary storage device having a plurality of storage units for storing and reading video signals selectively supplied thereto by a coupling circuit. An alternate storage device functions as a backup and receives and stores all of the video signals that are supplied to the primary storage device; and reads out therefrom the video signals which are in the process of being read from the primary storage device in the event a failure is detected in the primary storage device.
摘要翻译：用于发送视频信号的设备包括具有多个存储单元的主存储设备，用于存储和读取由耦合电路选择性地提供给其的视频信号。备用存储设备用作备份，并接收并存储提供给主存储设备的所有视频信号; 并且在主存储装置中检测到故障的情况下读出正在从主存储装置读取的视频信号。

40. 发明授权

US5389810A Semiconductor device having at least one symmetrical pair of MOSFETs 失效
标题翻译：具有至少一对对称的MOSFET的半导体器件
公开(公告)号：US5389810A
公开(公告)日：1995-02-14
申请号：US35731
申请日：1993-03-23
申请人： Masashi Agata , Hiroyuki Yamauchi , Toshio Yamada
发明人： Masashi Agata , Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088
摘要： A semiconductor device having at least one symmetrical pair of MOSFETs is provided. The device includes a semiconductor layer having an upper surface, an active region formed in the upper surface, an isolation region formed in the upper surface and enclosing the active region, and a pair of MOSFETs formed in the active region, wherein the pair of MOSFETs are symmetrical with respect to a first symmetric plane substantially vertical to the upper surface and also with respect to a second symmetric plane vertical both to the upper surface and to the first symmetric plane, each of the pair of MOSFETs includes a source region, a drain region, and a channel region formed in an upper surface of the active region, the source region is shared by the pair of MOSFETs, and the drain region is spatially isolated from the source region by the channel region.
摘要翻译：提供了具有至少一对对称的MOSFET的半导体器件。该器件包括具有上表面的半导体层，形成在上表面中的有源区，形成在上表面并包围有源区的隔离区，以及形成在有源区中的一对MOSFET，其中，所述一对MOSFET 相对于基本上垂直于上表面的第一对称平面以及垂直于上表面和第一对称平面的第二对称平面是对称的，所述一对MOSFET中的每一个包括源极区域，漏极区域和形成在有源区的上表面中的沟道区域，源极区域被该对MOSFET共享，并且漏极区域通过沟道区域与源极区域空间隔离。

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