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    • 32. 发明申请
    • PROCESSING DEVICE
    • 加工设备
    • US20070174591A1
    • 2007-07-26
    • US11277622
    • 2006-03-28
    • Hiroyuki SaitohTakeshi Nishidoi
    • Hiroyuki SaitohTakeshi Nishidoi
    • G06F11/00
    • G06F11/18G06F11/3433G06F15/16G06F2201/81G06F2201/87
    • A transaction input/output CPU receives a transaction to be processed and outputs the execution result of the transaction. A plurality of processing CPUs execute the transaction according to an instruction from the transaction input/output CPU. A plurality of memory areas are related to each processing CPU and store a transaction which are inputted to the transaction input/output CPU and its execution result. A register stores a pointer for indicating an address common to the plurality of memory areas. The processing CPU reads a pointer from the register, and reads a transaction from the storage destination in memory corresponding to each processing CPU and executes it.
    • 交易输入/输出CPU接收要处理的交易,并输出交易的执行结果。 多个处理CPU根据交易输入/输出CPU的指令执行交易。 多个存储区域与每个处理CPU相关,并存储输入到交易输入/输出CPU的交易及其执行结果。 寄存器存储用于指示多个存储区域共用的地址的指针。 处理CPU从寄存器读取指针,并从与每个处理CPU对应的存储器中的存储目的地读取事务并执行。
    • 35. 发明授权
    • Interrupt process distributing system
    • 中断流程分配系统
    • US5805883A
    • 1998-09-08
    • US815071
    • 1997-03-11
    • Hiroyuki Saitoh
    • Hiroyuki Saitoh
    • G06F15/16G06F9/46G06F13/24G06F15/163G06F15/177
    • G06F13/24
    • An interrupt process distributing system, provided in a CPU board in a loose-coupled type multiprocessor system formed of a plurality of CPU boards and one I/O board which are interconnected through common mediation and interrupt busses. A CPU executes interrupt requests; a queue counter, connected to the CPU through an internal bus, counts the interrupt requests which are sent from the common bus to and queued in the CPU. An interrupt transfer control unit, connected to the CPU and the queue counter through the internal bus, counts the interrupt requests as received from the interrupt bus, compares the number of queued interrupts with the number of received interrupt requests, and transfers the received interrupt requests to the CPU when the number of the received interrupt requests exceeds the number of queued interrupt requests.
    • 一种中断处理分配系统,其设置在由多个CPU板组成的松散耦合型多处理器系统中的CPU板和通过共同中介和中断总线相互连接的一个I / O板之间。 CPU执行中断请求; 通过内部总线连接到CPU的队列计数器对从公共总线发送到CPU并排队的中断请求进行计数。 通过内部总线连接到CPU和队列计数器的中断传输控制单元对从中断总线接收到的中断请求进行计数,将排队中断数与接收到的中断请求数进行比较,并传送接收到的中断请求 当接收到的中断请求的数量超过排队的中断请求数时,CPU被发送到CPU。