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31. 发明授权

US07586143B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07586143B2
公开(公告)日：2009-09-08
申请号：US11339701
申请日：2006-01-26
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L27/108
CPC分类号： H01L21/486 , H01L23/5223 , H01L23/5226 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.
摘要翻译：基板在第一布线层111上设置有第一布线层111，层间绝缘膜132，形成在层间绝缘膜中的孔112A，覆盖孔112A的第一金属层112，形成在第一布线层111上的第二金属层113 孔112A，第一金属层112上的介电绝缘膜135和介电绝缘膜135上的第二布线层114-116，其中第一金属层112构成下电极的至少一部分，面向第二布线层114-116的下电极构成上电极，电容器160由下电极，电介质绝缘膜135和上电极P1构成。

32. 发明授权

US07538023B2 Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area 有权
标题翻译：制造在周边区域具有分离的导电图案的半导体晶片装置的方法
公开(公告)号：US07538023B2
公开(公告)日：2009-05-26
申请号：US11519052
申请日：2006-09-12
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L21/76828 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L2221/1036 , H01L2924/0002 , H01L2924/12044 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.
摘要翻译：一种制造半导体晶片装置的方法包括以下步骤：（a）在半导体晶片上形成较低的布线图案，所述下布线图案与电路区域中的半导体元件连接; （b）在半导体晶片上形成具有平坦化表面的层间绝缘膜，覆盖下布线图案并具有平坦化表面; 和（c）通过嵌入通孔导体，布线连接到电路区域中连接到下布线图案和配置在通路导体上的布线图案的通孔导体和对应于电路区域以外的周边区域中的布线图案的导体图案图案和导体图案，导电图案是电隔离的。该方法可以形成期望的布线结构，并且可以防止有效晶片区域中的有缺陷的器件的百分比的增加。

33. 发明授权

US07484890B2 Rolling slide member 失效
标题翻译：滚动滑动构件
公开(公告)号：US07484890B2
公开(公告)日：2009-02-03
申请号：US11247586
申请日：2005-10-12
申请人： Takaaki Ikeda , Yoshiaki Sakaki , Kazuyoshi Kurihara , Yoshitaka Waseda , Masanori Setsuda , Kenichi Watanabe
发明人： Takaaki Ikeda , Yoshiaki Sakaki , Kazuyoshi Kurihara , Yoshitaka Waseda , Masanori Setsuda , Kenichi Watanabe
IPC分类号： F16C33/58 , F16C33/64 , B21K1/02 , B24B1/00
CPC分类号： F16H53/06 , F16C13/006 , F16C33/34 , F16C2240/54 , Y10T29/49679
摘要： There is provided a rolling slide member coming in contact with a mating member in a rolling or sliding manner, wherein a plurality of grooves having an inclination of 0 to 30 degree and a groove depth of 0.5 to 15 μm are formed in a circumferential direction at the time of grinding a contact surface with the mating member. In the contact surface, the axial surface waviness is set to 0.1 or more in the filtered centerline waviness (WCA) and the axial surface roughness is set to 0.7 or more in the ten-point height of roughness profile (Rz) by the grooves 26.
摘要翻译：提供了一种滚动滑动构件，其以滚动或滑动方式与配合构件接触，其中在圆周方向上形成具有0至30度的倾斜度和0.5至15μm的凹槽深度的多个凹槽研磨与配合构件的接触表面的时间。在接触表面中，在过滤的中心线波纹（WCA）中将轴向表面波纹度设定为0.1以上，并且通过槽26在粗糙度轮廓（Rz）的十点高度中将轴向表面粗糙度设定为0.7以上。

34. 发明授权

US07375170B2 Organosilicon compound 有权
标题翻译：有机硅化合物
公开(公告)号：US07375170B2
公开(公告)日：2008-05-20
申请号：US11316847
申请日：2005-12-27
申请人： Hisao Oikawa , Mikio Yamahiro , Koji Ohguma , Nobumasa Ootake , Kenichi Watanabe , Kohji Ohno , Yoshinobu Tsujii , Takeshi Fukuda
发明人： Hisao Oikawa , Mikio Yamahiro , Koji Ohguma , Nobumasa Ootake , Kenichi Watanabe , Kohji Ohno , Yoshinobu Tsujii , Takeshi Fukuda
IPC分类号： C08F4/58
CPC分类号： C07F7/21
摘要： Since the majority of conventional organic/inorganic composite materials are obtained by mechanical blending of a silsesquioxane and an organic polymer or other means, it was extremely difficult to control the structure of the composite as a molecular agglomerate. In order to solve such a problem, the invention is to provide a silicon compound represented by Formula (1). This novel silicon compound has a living radical polymerization initiating ability for addition polymerizable monomers of a wide range. In Formula (1), R1 is hydrogen, an alkyl, an aryl, or an arylalkyl; R2 is an alkyl, phenyl, or cyclohexyl; and A is a group having a polymerization initiating ability for addition polymerizable monomers
摘要翻译：由于大多数常规的有机/无机复合材料是通过机械共混倍半硅氧烷和有机聚合物或其它方法获得的，所以非常难以控制复合材料的结构作为分子聚集体。为了解决这个问题，本发明提供一种由式（1）表示的硅化合物。该新型硅化合物具有广泛范围的可加聚单体的活性自由基聚合引发能力。在式（1）中，R 1是氢，烷基，芳基或芳基烷基; R 2是烷基，苯基或环己基; A是具有加成聚合性单体的聚合引发能力的基团

35. 发明申请

US20080012147A1 Semiconductor device for preventing defective filling of interconnection and cracking of insulating film 有权
标题翻译：用于防止缺陷填充互连和绝缘膜破裂的半导体装置
公开(公告)号：US20080012147A1
公开(公告)日：2008-01-17
申请号：US11898548
申请日：2007-09-13
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L23/48
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
摘要翻译：半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及掩埋在孔形通孔60和槽形通孔66a中的埋入导体70,72a。形成沟槽状的通孔66a的宽度小于孔状的通路孔66的宽度。可以防止掩埋导体的不充分填充和层间绝缘膜的开裂。导体插头上的步骤可以减少。因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

36. 发明授权

US07119439B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07119439B2
公开(公告)日：2006-10-10
申请号：US10454667
申请日：2003-06-05
申请人： Kenichi Watanabe , Michiari Kawano
发明人： Kenichi Watanabe , Michiari Kawano
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L21/76847 , H01L21/76852 , H01L23/53238 , H01L23/564 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.

37. 发明授权

US07119009B2 Semiconductor device with dual damascene wiring 有权
公开(公告)号：US07119009B2
公开(公告)日：2006-10-10
申请号：US10898938
申请日：2004-07-27
申请人： Kenichi Watanabe , Daisuke Komada , Fumihiko Shimpuku
发明人： Kenichi Watanabe , Daisuke Komada , Fumihiko Shimpuku
IPC分类号： H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76807 , H01L21/76813 , H01L21/76829 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

38. 发明授权

US07067919B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07067919B2
公开(公告)日：2006-06-27
申请号：US10309113
申请日：2002-12-04
申请人： Kenichi Watanabe , Noriyoshi Shimizu , Takashi Suzuki
发明人： Kenichi Watanabe , Noriyoshi Shimizu , Takashi Suzuki
IPC分类号： H01L23/48
CPC分类号： H01L21/76811 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.
摘要翻译：一种半导体器件，包括形成在第一布线的表面和第一绝缘膜的表面上的基本上平坦的表面上的第二绝缘膜，以覆盖第一布线;形成在第二绝缘膜中的布线沟槽，在第二绝缘膜上形成的连接孔从布线沟槽延伸到第一布线，形成在第二绝缘膜中的虚拟连接孔从布线沟槽延伸到第一布线的非形成区域，第二布线埋入在与第一布线电连接并连接在虚拟连接孔中的连接孔和布线沟槽中，并且形成为使得第二布线的表面和第二绝缘膜的表面构成基本平坦的表面。

39. 发明申请

US20060089504A1 Silsesquioxane derivative having functional group 审中-公开
标题翻译：具有官能团的倍半硅氧烷衍生物
公开(公告)号：US20060089504A1
公开(公告)日：2006-04-27
申请号：US11294364
申请日：2005-12-06
申请人： Kenya Ito , Mikio Yamahiro , Kenichi Watanabe
发明人： Kenya Ito , Mikio Yamahiro , Kenichi Watanabe
IPC分类号： C07F7/10
CPC分类号： C08G77/06 , C08G77/045 , C08G77/38
摘要： A conventional silsesquioxane derivative has the problems that the functional groups are restricted and the chemical structure is not readily controlled and that it is expensive. The present inventors have developed a process for producing a silsesquioxane derivative at a high yield by a simple process in order to solve such problems. The novel silsesquioxane derivative according to the present invention is controlled in a structure thereof and has a functional group, which is excellent in reactivity with a target compound, to be modified. The present invention relates to a production process for a silsesquioxane derivative represented by Formula (2), characterized by using a silicon compound represented by Formula (1). In Formula (1) and Formula (2), R is a group selected from hydrogen, alkyl, aryl and arylalkyl; M is a monovalent alkaline metal atom; at least one of Y is a group represented by Formula (3), and the remainder of Y is hydrogen; R1 and R2 in Formula (3) represent the same group as defined for R; and Z is a functional group or a group having a functional group.
摘要翻译：常规的倍半硅氧烷衍生物存在官能团受限并且化学结构不容易控制并且昂贵的问题。为了解决这些问题，本发明人通过简单的工艺开发了高产率的倍半硅氧烷衍生物的制备方法。根据本发明的新型倍半硅氧烷衍生物在其结构中被控制，并且具有与待改性的目标化合物的反应性优异的官能团。本发明涉及由式（2）表示的倍半硅氧烷衍生物的制备方法，其特征在于使用由式（1）表示的硅化合物。在式（1）和式（2）中，R是选自氢，烷基，芳基和芳基烷基的基团; M是一价碱性金属原子; Y中的至少一个为由式（3）表示的基团，Y的其余部分为氢; 式（3）中的R 1和R 2代表与R所定义的相同的基团; Z为官能团或具有官能团的基团。

40. 发明申请

US20050285271A1 Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area 有权
标题翻译：制造在周边区域具有分离的导电图案的半导体晶片装置的方法
公开(公告)号：US20050285271A1
公开(公告)日：2005-12-29
申请号：US11175314
申请日：2005-07-07
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L21/76828 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L2221/1036 , H01L2924/0002 , H01L2924/12044 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.
摘要翻译：一种制造半导体晶片装置的方法包括以下步骤：（a）在半导体晶片上形成较低的布线图案，所述下布线图案与电路区域中的半导体元件连接; （b）在半导体晶片上形成具有平坦化表面的层间绝缘膜，覆盖下布线图案并具有平坦化表面; 和（c）通过嵌入通孔导体，布线连接到电路区域中连接到下布线图案和配置在通路导体上的布线图案的通孔导体和对应于电路区域以外的周边区域中的布线图案的导体图案图案和导体图案，导电图案是电隔离的。该方法可以形成期望的布线结构，并且可以防止有效晶片区域中的有缺陷的器件的百分比的增加。

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