专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5623454A Semiconductor memory device 失效
公开(公告)号：US5623454A
公开(公告)日：1997-04-22
申请号：US599265
申请日：1996-02-09
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

32. 发明授权

US5521878A Clock synchronous semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US5521878A
公开(公告)日：1996-05-28
申请号：US305522
申请日：1994-09-12
申请人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
发明人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
IPC分类号： G11C11/41 , G06F12/08 , G11C7/10 , G11C7/22 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1072 , G11C11/005 , G11C11/4076 , G11C11/4096 , G11C7/103 , G11C7/1051 , G11C7/22
摘要： A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
摘要翻译：当外部时钟信号Ka处于非活动状态时，信号输入缓冲器达到通过状态，并且响应于外部信号产生内部信号，并且当外部时钟信号处于非活动状态时，信号输入缓冲器达到锁存状态。响应于正在使用的从属数据寄存器的检测，执行从通过从属数据寄存器将数据存储在DRAM阵列中的主数据寄存器的数据传送。从数据寄存器存储要传输到SRAM阵列的数据或要外部访问的数据。因此，提供了可高速访问并且不等待的同步半导体存储器件。此外，响应于外部时钟信号的激活，内部时钟信号被激活预定时间以确保精确的内部操作定时。

33. 发明授权

US5184321A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列
公开(公告)号：US5184321A
公开(公告)日：1993-02-02
申请号：US821875
申请日：1992-01-16
申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074 , G11C11/408
CPC分类号： G11C11/4074 , G11C11/408 , Y10S257/92
摘要： A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.
摘要翻译：多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。多个存储器阵列（10a，10b）由预定层形成（101差异109）。要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。多个互连（L）由除预定的互连层之外的层（112; 113）形成。

34. 发明授权

US4961167A Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein 失效
标题翻译：具有自动/自刷新功能的动态随机存取存储器中的衬底偏置发生器及其中产生衬底偏置的方法
公开(公告)号：US4961167A
公开(公告)日：1990-10-02
申请号：US381347
申请日：1989-07-18
申请人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074
CPC分类号： G11C11/4074
摘要： A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.
摘要翻译：一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93）使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99）对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。上述结构有助于动态随机存取存储器中的功耗降低。

35. 发明授权

US4961007A Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor 失效
标题翻译：半导体集成电路器件的衬底偏置电位发生器及其生成方法
公开(公告)号：US4961007A
公开(公告)日：1990-10-02
申请号：US337218
申请日：1989-04-12
申请人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Youichi Tobita
发明人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Youichi Tobita
IPC分类号： G11C11/408 , G05F3/20 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： G05F3/205 , H02M3/07
摘要： A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential generator is reduced. The alternative operation of the bias generating circuits each activated by a pulse signal train is performed by using a first insulated gate transistor having a gate electrode connected to the semiconductor substrate, a second insulated gate transistor having a gate electrode for receiving the reference potential, an amplifier for differentially amplifying outputs of the first and second insulated gate transistors, an insulated gate transistor for charging an output of the amplifier to a predetermined potential when the amplifier is activated, and a circuit for transmitting the output of the differential amplifier to the first and second bias potential generating circuits. The differential amplifier is activated in response to an activation signal of a pulse train whereby an activation signal corresponding to the pulse train is transmitted to either substrate bias potential generating circuit.
摘要翻译：用于将半导体衬底偏置到预定电位的衬底偏置电位发生器包括根据衬底的电位交替地操作的第一和第二衬底偏置产生电路，由此降低衬底偏置电位发生器中的功率消耗。通过使用具有连接到半导体衬底的栅电极的第一绝缘栅极晶体管，具有用于接收参考电位的栅电极的第二绝缘栅极晶体管，执行由脉冲信号列激活的偏置产生电路的替代操作，放大器，用于差分放大第一和第二绝缘栅极晶体管的输出;绝缘栅极晶体管，用于在放大器被激活时将放大器的输出充电到预定电位;以及电路，用于将差分放大器的输出传输到第一和第二绝缘栅极晶体管，第二偏置电位发生电路。差分放大器响应于脉冲串的激活信号被激活，由此将对应于脉冲串的激活信号传输到任一衬底偏置电位产生电路。

36. 发明授权

US4933907A Dynamic random access memory device and operating method therefor 失效
标题翻译：动态随机存取存储器及其操作方法
公开(公告)号：US4933907A
公开(公告)日：1990-06-12
申请号：US278552
申请日：1988-12-01
申请人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Hiroyuki Yamasaki , Takahiro Komatsu , Yoichi Tobita
发明人： Masaki Kumanoya , Katsumi Dosaka , Yasuhiro Konishi , Hiroyuki Yamasaki , Takahiro Komatsu , Yoichi Tobita
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/406
摘要： A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the self-refresh mode. As a result, each group in the memory array is refreshed at a time interval of two times a conventional refresh interval, so that the power consumption is decreased.
摘要翻译：具有自刷新模式的动态随机存取存储器包括分为四组的存储器阵列，其中分别执行控制和部分激活控制电路。存储器阵列中的四组在自刷新模式下的操作中被两个两个地刷新。结果，存储器阵列中的每个组以传统刷新间隔的两倍的时间间隔被刷新，使得功耗降低。

37. 发明授权

US4736343A Dynamic RAM with active pull-up circuit 失效
标题翻译：具有主动上拉电路的动态RAM
公开(公告)号：US4736343A
公开(公告)日：1988-04-05
申请号：US929370
申请日：1986-11-12
申请人： Hideto Hidaka , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Katsumi Dosaka , Yasuhiro Konishi
发明人： Hideto Hidaka , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Katsumi Dosaka , Yasuhiro Konishi
IPC分类号： G11C11/409 , G11C7/12 , G11C11/4094 , G11C11/24
CPC分类号： G11C11/4094 , G11C7/12
摘要： 44Gate potentials of transistors Q.sub.R0 and Q.sub.R1 provided in an active pull-up circuit APo are always controlled to be appropriate values by a clock signal .phi..sub.p. As a result, reverse flow of electric charge from a capacitor C.sub.R0 or C.sub.R1 to a bit line LB or BL can be prevented and unfavorable influence due to such reverse flow of electric charge can be avoided in operation of the active pull-up circuit APo.
摘要翻译：在主动上拉电路APo中提供的晶体管QR0和QR1的栅极电位总是通过时钟信号phi被控制为适当的值。结果，可以防止从电容器CR0或CR1到位线LB或＆amp; upbar＆B的电荷的反向流动，并且在有源上拉电路APo的操作中可以避免由于这种反向电荷的不利影响。

38. 发明授权

US4730320A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4730320A
公开(公告)日：1988-03-08
申请号：US825869
申请日：1986-02-04
申请人： Hideto Hidaka , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Katsumi Dosaka , Tsutomu Yoshihara
发明人： Hideto Hidaka , Kazuyasu Fujishima , Masaki Kumanoya , Hideshi Miyatake , Katsumi Dosaka , Tsutomu Yoshihara
IPC分类号： G06F11/10 , G06F11/267
CPC分类号： G06F11/2215 , G06F11/1008 , G06F11/1076
摘要： A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.
摘要翻译：半导体存储器件包括连接在写入校验位产生电路（2）的输出侧和校验位存储单元阵列（32）的输入侧之间的数据输入切换电路（20），数据输出切换电路（30））和连接到地址解码器（9）的输出侧的地址切换电路（10）。当输入测试模式时，数据输入切换电路（2），数据输出切换电路（30）和地址切换电路（10）连接数据输入信号线（l），数据输出信号线（m）和地址信号（n）分配给校验位存储单元阵列（32），从而能够从外部访问校验位存储单元阵列（32）。

39. 发明授权

US08638583B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08638583B2
公开(公告)日：2014-01-28
申请号：US13621078
申请日：2012-09-15
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00 , G11C15/04 , G11C7/14 , G11C7/06 , G11C7/12 , G11C7/22
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

40. 发明授权

US08169807B2 Content addressable memory device having match line equalizer circuit 有权
标题翻译：具有匹配线均衡器电路的内容可寻址存储器件
公开(公告)号：US08169807B2
公开(公告)日：2012-05-01
申请号：US12261598
申请日：2008-10-30
申请人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
发明人： Katsumi Dosaka , Kazutami Arimoto , Yoshio Matsuda
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then connects the first and second match lines to each other so as that electric potentials of the first and second match lines are the same as each other.
摘要翻译：在内容可寻址存储器件中，在分别连接到第一和第二匹配线的两个TCAM单元中的搜索操作之前，存储器控制器将第一匹配线连接到电源，并将第二匹配线连接到地，然后将第一和第二匹配线彼此之间，使得第一和第二匹配线的电位彼此相同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式