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31. 发明授权

US08144726B2 Structure for out of band signaling enhancement for high speed serial driver 有权
标题翻译：用于高速串行驱动程序的带外信令增强的结构
公开(公告)号：US08144726B2
公开(公告)日：2012-03-27
申请号：US12154796
申请日：2008-05-27
申请人： Huihao Xu , Joseph Natonio , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Joseph Natonio , James D. Rockrohr , Michael A. Sorna
IPC分类号： H04L12/43 , G06F17/50
CPC分类号： G06F13/4295
摘要： A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.
摘要翻译：为微电子串行驱动器提供了一种设计结构。串行驱动器可操作以在相邻突发间隔期间的第二间隔期间在突发间隔期间和预定共模电压电平期间发送差分模式信号，该串行驱动器包括至少一个预驱动器和耦合到该输出的驱动器用于发送差分通信信号的预驱动器。开关电路可操作以在脉冲串间隔的第一电源电压电平和预定共模电压电平之间切换串行驱动器，其中预定共模电压电平与电源电压条件和温度条件的变化无关。

32. 发明授权

US08410835B1 Leakage tolerant phase locked loop circuit device 有权
标题翻译：泄漏容限锁相环电路器件
公开(公告)号：US08410835B1
公开(公告)日：2013-04-02
申请号：US13342453
申请日：2012-01-03
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/101 , H03L7/0891 , H03L7/093
摘要： Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.
摘要翻译：提供了泄漏容限锁相环（PLL）电路装置以及使用泄漏容限PLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括PLL电路装置，其包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器，压控振荡器（VCO）和反馈分压器。二次校正电路被配置为产生并向误差控制器提供次级错误频率信号。二次校正电路被配置为响应于检测到分压的VCO输出信号的特定边缘而产生次级错误频率信号。主回路被配置为基于第一误差频率增大信号，第一误差 - 频率降低信号和次级错误频率信号中的至少一个来控制频率调整。

33. 发明申请

US20110199843A1 Strobe Offset in Bidirectional Memory Strobe Configurations 有权
标题翻译：双向内存频闪配置中的频闪偏移
公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

34. 发明申请

US20100054324A1 SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS 有权
标题翻译：在决策反馈均衡器中减少衰减的系统和方法
公开(公告)号：US20100054324A1
公开(公告)日：2010-03-04
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译：决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

35. 发明申请

US20090128161A1 Structure for robust cable connectivity test receiver for high-speed data receiver 有权
标题翻译：用于高速数据接收机的坚固电缆连接测试接收机的结构
公开(公告)号：US20090128161A1
公开(公告)日：2009-05-21
申请号：US11985956
申请日：2007-11-19
申请人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
发明人： Huihao Xu , Louis L. Hsu , Kevin G. Kramer , James D. Rockrohr , Michael A. Sorna
IPC分类号： H04B3/46
CPC分类号： G06F11/24
摘要： A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构可以包括用于检测信号传输路径中的故障的系统。这种系统可以包括例如包括具有n型场效应晶体管（“NFET”）存储元件的锁存器的滞后比较器。滞后比较器可以用于检测参考电压电平与从信号传输路径到达的输入信号的交叉，使得当比较器没有检测到参考电压电平与输入信号的预期交叉时，确定故障以在信号传输路径中被检测。

36. 发明申请

US20080061825A1 CML TO CMOS SIGNAL CONVERTER 失效
标题翻译： CML TO CMOS信号转换器
公开(公告)号：US20080061825A1
公开(公告)日：2008-03-13
申请号：US11467349
申请日：2006-08-25
申请人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
发明人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译：提供信号再生器，其包括共模参考发生器和信号转换器电路。产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变模式参考发生器运行。信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。

37. 发明授权

US06785832B2 Process independent source synchronous data capture apparatus and method 有权
标题翻译：过程独立源同步数据采集设备和方法
公开(公告)号：US06785832B2
公开(公告)日：2004-08-31
申请号：US09887792
申请日：2001-06-22
申请人： Leonard R. Chieco , Louis T. Fasano , Michael A. Sorna
发明人： Leonard R. Chieco , Louis T. Fasano , Michael A. Sorna
IPC分类号： G06F112
CPC分类号： H04L7/0008
摘要： An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.
摘要翻译：一种用于捕获从发送源发送到接收元件的数据信号的装置，所述数据信号伴随着源同步系统中的第一时钟信号。在示例性实施例中，该装置包括具有耦合到第一时钟信号的输入和产生延迟的第一时钟信号的输出的延迟元件。延迟元件还包括多个延迟锁存器，其具有作为其输入的时钟的第二时钟信号，第二时钟信号的频率是第一时钟信号的频率的倍数。当接收元件被延迟的第一时钟信号的边沿触发时，接收元件捕获数据信号。

38. 发明授权

US06661267B2 Coarse calibration circuit using variable step sizes to reduce jitter and a dynamic course calibration (DCC) circuit for a 2 GHz VCO 失效
标题翻译：使用可变步长的粗校准电路可以减少2 GHz VCO的抖动和动态校准（DCC）电路
公开(公告)号：US06661267B2
公开(公告)日：2003-12-09
申请号：US10139931
申请日：2002-05-06
申请人： Norman Hugo Walker , Victor Moy , Allan Leslie Mullgrav, Jr. , Michael A. Sorna
发明人： Norman Hugo Walker , Victor Moy , Allan Leslie Mullgrav, Jr. , Michael A. Sorna
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/099 , H03L7/183 , H03L2207/06
摘要： A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.
摘要翻译：用于锁相环（PLL）的校准系统包括耦合到压控振荡器（VCO）的输出和参考频率源的相位/频率检测器。连接电荷泵以接收来自相位/频率检测器的误差信号，并向低通滤波器提供电压。低通滤波器向VCO和比较器系统提供滤波后的误差信号。比较器系统提供比较器输出信号，指示误差信号的极性何时超过正极限或负极限。校准装置在经过时间延迟之后，连续向VCO提供增量校准输入。因此，PLL中的VCO的频率被连续校正以补偿频率漂移，并且避免由对校准输入的响应过大引起的抖动。

39. 发明申请

US20130120041A1 Leakage Tolerant Delay Locked Loop Circuit Device 有权
标题翻译：泄漏容限延迟锁定环路电路装置
公开(公告)号：US20130120041A1
公开(公告)日：2013-05-16
申请号：US13295351
申请日：2011-11-14
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/0816
摘要： Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.
摘要翻译：提供了泄漏容限延迟锁定环（DLL）电路装置以及使用泄漏容限DLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括DLL电路装置，包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器和压控缓冲器（VCB）。二次校正电路被配置为产生并向误差控制器提供二次误差延迟信号。二次校正电路包括多个误差发生器。响应于检测到来自VCB的输出相位信号的特定边缘，每个误差发生器被配置为产生二次误差延迟信号。主回路被配置为基于第一误差延迟增加信号，第一误差延迟降低信号和次级误差延迟信号中的至少一个来控制相位调整。

40. 发明授权

US08126045B2 System and method for latency reduction in speculative decision feedback equalizers 有权
标题翻译：投机决策反馈均衡器延迟降低的系统和方法
公开(公告)号：US08126045B2
公开(公告)日：2012-02-28
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译：决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

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