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31. 发明授权

US07893726B1 Leakage compensation and improved setup/hold time in a dynamic flip-flop 有权
标题翻译：在动态触发器中泄漏补偿和改进的设置/保持时间
公开(公告)号：US07893726B1
公开(公告)日：2011-02-22
申请号：US11782443
申请日：2007-07-24
申请人： Vinh Van Ho , Tim Tri Hoang
发明人： Vinh Van Ho , Tim Tri Hoang
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G11C11/412 , H03K3/012 , H03K3/356139
摘要： A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
摘要翻译：动态触发器包括形成适于接收差分数据的差分输入级的第一和第二输入级。触发器响应于复位信号被复位。为了确保正常操作，设置在第一和第二输入级之间的晶体管总是保持有效，以在接地端子和节点之间提供可以从电源电压充电的导电路径。为了改善触发器的设置和保持时间，时钟信号被施加到设置在第一输入级中的第一晶体管和设置在第二输入级中的第二晶体管。

32. 发明授权

US07659745B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07659745B1
公开(公告)日：2010-02-09
申请号：US12218688
申请日：2008-07-16
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

33. 发明授权

US07590207B1 Modular serial interface in programmable logic device 有权
标题翻译：可编程逻辑器件中的模块化串行接口
公开(公告)号：US07590207B1
公开(公告)日：2009-09-15
申请号：US11256346
申请日：2005-10-20
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.
摘要翻译：用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环）。这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

34. 发明授权

US07495517B1 Techniques for dynamically adjusting the frequency range of phase-locked loops 有权
标题翻译：用于动态调整锁相环频率范围的技术
公开(公告)号：US07495517B1
公开(公告)日：2009-02-24
申请号：US11610892
申请日：2006-12-14
申请人： Tim Tri Hoang , Sergey Shumarayev
发明人： Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03L7/06 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/18
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/093 , H03L7/095 , H03L7/099 , Y10S331/02
摘要： Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.
摘要翻译：提供了用于动态调整锁相环（PLL）频率范围的技术。 PLL中的相位检测电路响应于周期性输入信号和反馈信号产生控制信号。当控制信号偏离有效范围时，PLL的输入频率范围被动态地调整为包括周期性输入信号频率。通过改变PLL中的一个或多个频率比来调整PLL的输入频率范围。可以动态地调整PLL中的环路滤波器的电阻和/或电容，以控制PLL的带宽。

35. 发明授权

US07417462B1 Variable external interface circuitry on programmable logic device integrated circuits 失效
标题翻译：可编程逻辑器件集成电路上的可变外部接口电路
公开(公告)号：US07417462B1
公开(公告)日：2008-08-26
申请号：US11726174
申请日：2007-03-20
申请人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Wilson Wong , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03K5/00 , G06F7/38
CPC分类号： H03K19/17744
摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.
摘要翻译：可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的衰减。

36. 发明授权

US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features 有权
标题翻译：时钟和数据恢复电路，具有自动速度协商和其他可能的功能
公开(公告)号：US08811555B2
公开(公告)日：2014-08-19
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

37. 发明授权

US08416001B2 Techniques for reducing duty cycle distortion in periodic signals 有权
标题翻译：降低周期信号中占空比失真的技术
公开(公告)号：US08416001B2
公开(公告)日：2013-04-09
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

38. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

39. 发明授权

US07994837B1 Techniques for phase interpolation 有权
标题翻译：相位插值技术
公开(公告)号：US07994837B1
公开(公告)日：2011-08-09
申请号：US12537634
申请日：2009-08-07
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
IPC分类号： H03H11/16
CPC分类号： H03H11/22
摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.
摘要翻译：相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。相位内插器电路可以包括三个差分对的晶体管。具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

40. 发明授权

US07860203B1 High-speed serial data signal interface architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的高速串行数据信号接口架构
公开(公告)号：US07860203B1
公开(公告)日：2010-12-28
申请号：US11725653
申请日：2007-03-19
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.
摘要翻译：可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环（“PLL”）电路等）。为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

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