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    • 32. 发明授权
    • Memory cell configuration and corresponding production process
    • 内存单元配置及相应的生产流程
    • US06472696B1
    • 2002-10-29
    • US09645763
    • 2000-08-25
    • Ulrich ZimmermannThomas BöhmManfred HainArmin KohlhaseYoichi OtaniAndreas RuschAlexander Trüby
    • Ulrich ZimmermannThomas BöhmManfred HainArmin KohlhaseYoichi OtaniAndreas RuschAlexander Trüby
    • H01L2710
    • H01L27/11273H01L27/112
    • The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.
    • 存储单元配置具有设置在半导体衬底中的大量存储单元,并且具有在半导体衬底的主面中在纵向方向上平行延伸的位线沟槽,其底部在每种情况下都具有第一导电 区域被提供,其峰值在每种情况下具有与第一导电区域相同的导电类型的第二导电区域,并且在其每一种情况下壁的中间位置的沟道区域为0; 并且具有通过特定位线沟槽沿着半导体衬底的主面在横向上延伸的字线,以激活在其中设置的晶体管。 另外的掺杂剂被引入位于字线之间的位线沟槽的沟槽壁中,以便在其上增加对应的晶体管导通电压以抑制漏电流。