专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08972775B2 Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit 有权
标题翻译：存储器件和管理存储器数据错误的方法，包括基于校正的误差位确定验证电压和改变阈值电压
公开(公告)号：US08972775B2
公开(公告)日：2015-03-03
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/07 , G11C16/10 , G06F11/10 , G11C11/56 , G11C16/34 , G11C29/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

32. 发明授权

US08713411B2 Encoding and/or decoding memory devices and methods thereof 有权
标题翻译：编码和/或解码存储器件及其方法
公开(公告)号：US08713411B2
公开(公告)日：2014-04-29
申请号：US12232258
申请日：2008-09-12
申请人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
发明人： Jun Jin Kong , Yong June Kim , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/03 , G06F11/1072 , H03M13/05
摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.
摘要翻译：可以提供编码/解码存储器件及其方法。根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

33. 发明授权

US08347194B2 Hierarchical decoding apparatus 有权
标题翻译：分层解码装置
公开(公告)号：US08347194B2
公开(公告)日：2013-01-01
申请号：US12428511
申请日：2009-04-23
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： G06F11/00
CPC分类号： H03M13/2906 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/1194 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/296 , H03M13/3707 , H03M13/3738
摘要： A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
摘要翻译：解码器包括多个解码器级和控制器。解码器级使用相应的不同解码算法对接收到的信号执行解码操作。控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

34. 发明授权

US08284599B2 Nonvolatile memory device and related programming method 有权
标题翻译：非易失性存储器件及相关编程方法
公开(公告)号：US08284599B2
公开(公告)日：2012-10-09
申请号：US12786724
申请日：2010-05-25
申请人： Han Woong Yoo , Jae Hong Kim , Jun Jin Kong
发明人： Han Woong Yoo , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3427 , G11C2211/5648
摘要： A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.
摘要翻译：一种对非易失性存储器件进行编程的方法包括编程连接到第一字线的存储器单元，连接到第二字线的编程存储器单元，连接到第一字线和第二字线之间的第三线的编程存储器单元，以及调整阈值电压连接到第一字线的存储器单元以补偿由连接到第三字线的存储器单元的编程所产生的干扰。

35. 发明申请

US20100251077A1 STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME 审中-公开
标题翻译：存储设备和包括其的数据存储系统
公开(公告)号：US20100251077A1
公开(公告)日：2010-09-30
申请号：US12729285
申请日：2010-03-23
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.
摘要翻译：存储装置包括控制器单元和存储单元阵列。控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。第一存储器具有与第二存储器不同的存储单元结构。

36. 发明申请

US20090222701A1 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US20090222701A1
公开(公告)日：2009-09-03
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： G06F11/00 , G06F12/16
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

37. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

38. 发明授权

US08656258B2 Method of encoding and decoding multi-bit level data 有权
标题翻译：多位电平数据的编码和解码方法
公开(公告)号：US08656258B2
公开(公告)日：2014-02-18
申请号：US12429718
申请日：2009-04-24
申请人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong , Ki Jun Lee , Ha Bong Chung , Keun Sung Choi
发明人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong , Ki Jun Lee , Ha Bong Chung , Keun Sung Choi
IPC分类号： G06F11/00
CPC分类号： H03M13/451 , G06F11/1072
摘要： A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.
摘要翻译：一种编码多位电平数据的方法包括：根据传输符号确定产生的误差模式的范围，根据误差模式的范围来编码与发送符号对应的P位电平的M位电平，并且排除P位电平的PM位电平的编码。变量P是至少为2的值的自然数，变量M是小于P的自然数。

39. 发明授权

US08352808B2 Data storage system and device with randomizer/de-randomizer 有权
标题翻译：数据存储系统和具有随机化/去随机化器的设备
公开(公告)号：US08352808B2
公开(公告)日：2013-01-08
申请号：US12573246
申请日：2009-10-05
申请人： Yong June Kim , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho
发明人： Yong June Kim , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G06F11/1008
摘要： A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.
摘要翻译：数据存储装置接收写入数据，并且包括控制器，被配置为确定写入数据的特性并响应于所确定的特性提供第一控制信号;随机化器，被配置为响应于第一个数据，选择性地随机化或不使写入数据随机化从而生成随机写入数据，以及数据存储单元，被配置为存储随机写入数据。

40. 发明授权

US08345487B2 Method of setting read voltage minimizing read data errors 有权
标题翻译：设置读取电压最小化读取数据错误的方法
公开(公告)号：US08345487B2
公开(公告)日：2013-01-01
申请号：US12774814
申请日：2010-05-06
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son , Seung-Hwan Song
IPC分类号： G11C11/413
CPC分类号： G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
摘要翻译：一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式