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31. 发明授权

US08413098B2 T-connections, methodology for designing T-connections, and compact modeling of T-connections 失效
标题翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模
公开(公告)号：US08413098B2
公开(公告)日：2013-04-02
申请号：US12431887
申请日：2009-04-29
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, Jr.
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , G06F17/5036 , G06F17/5063 , G06F17/5072 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.
摘要翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分交界处并且其中T形结和台阶结的顶表面是共面的。

32. 发明申请

US20090249610A1 METHODS OF FABRICATING COPLANAR WAVEGUIDE STRUCTURES 有权
标题翻译：制备共振波导结构的方法
公开(公告)号：US20090249610A1
公开(公告)日：2009-10-08
申请号：US12061861
申请日：2008-04-03
申请人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
发明人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
IPC分类号： H01P11/00
CPC分类号： H01P11/003 , H01P3/003 , Y10T29/49016 , Y10T29/49155 , Y10T29/49162
摘要： Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.
摘要翻译：制造共面波导结构的方法。该方法可以包括在第一和第二接地导体之间的共面布置中形成第一和第二接地导体和信号导体，在信号导体和第一和第二接地导体之上形成基本上平行的屏蔽导体的第一共面阵列，并形成在信号导体和第一和第二接地导体下面的基本上平行的屏蔽导体的第二共面阵列。该方法还包括形成位于信号导体和第一接地导体之间横向定位的第一多个导电桥，以及形成位于信号导体和第二接地导体之间横向定位的第二多个导电桥。第一多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。第二多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。

33. 发明授权

US08028406B2 Methods of fabricating coplanar waveguide structures 有权
标题翻译：制造共面波导结构的方法
公开(公告)号：US08028406B2
公开(公告)日：2011-10-04
申请号：US12061861
申请日：2008-04-03
申请人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
发明人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
IPC分类号： H05K3/10 , H01P11/00 , H01P3/00
CPC分类号： H01P11/003 , H01P3/003 , Y10T29/49016 , Y10T29/49155 , Y10T29/49162
摘要： Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.
摘要翻译：制造共面波导结构的方法。该方法可以包括在第一和第二接地导体之间的共面布置中形成第一和第二接地导体和信号导体，在信号导体和第一和第二接地导体之上形成基本上平行的屏蔽导体的第一共面阵列，并形成在信号导体和第一和第二接地导体下面的基本上平行的屏蔽导体的第二共面阵列。该方法还包括形成位于信号导体和第一接地导体之间横向定位的第一多个导电桥，以及形成位于信号导体和第二接地导体之间横向定位的第二多个导电桥。第一多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。第二多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。

34. 发明申请

US20100276809A1 T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS 失效
标题翻译： T型连接，T型连接方法和T型连接的紧凑型建模
公开(公告)号：US20100276809A1
公开(公告)日：2010-11-04
申请号：US12431887
申请日：2009-04-29
申请人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, JR.
发明人： Hanyi Ding , Essam Mina , Guoan Wang , Wayne Harvey Woods, JR.
IPC分类号： H01L23/535 , G06F17/50 , G06F17/10
CPC分类号： H01L23/5225 , G06F17/5036 , G06F17/5063 , G06F17/5072 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.
摘要翻译： T型连接，T型连接的设计方法和T型连接的紧凑建模。 T形连接件包括一个导电T形接头，它包括主体和从本体的相互垂直的侧面突出的第一，第二和第三整体臂，三个整体臂的每个臂具有与主体相邻的相同的第一宽度和相同的长度远离身体; 导电性阶梯结，其包括具有第一宽度的第一部分和具有第二宽度的整体和邻接的第二部分，所述第二宽度不同于所述第一宽度，所述第一部分平滑地抵接并与所述第二部分交界处并且其中T形结和台阶结的顶表面是共面的。

35. 发明授权

US08592876B2 Micro-electro-mechanical system (MEMS) capacitive OHMIC switch and design structures 有权
标题翻译：微机电系统（MEMS）电容OHMIC开关和设计结构
公开(公告)号：US08592876B2
公开(公告)日：2013-11-26
申请号：US13342689
申请日：2012-01-03
申请人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
发明人： Hanyi Ding , Qizhi Liu , Anthony K. Stamper
IPC分类号： H01L29/80
CPC分类号： H01H1/0036 , B81B7/0006 , B81B2201/016 , G06F17/5063 , G06F17/5068 , H01P1/127
摘要： A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.
摘要翻译：提供了微机电系统（MEMS），形成MEMS和设计结构的方法。该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。该方法包括在绝缘体材料中形成至少一个通气孔以暴露第二牺牲材料的部分，以及通过通气孔去除第一和第二牺牲材料，以形成围绕布线层的空腔结构，并使信号线和一对电极在布线层下方。通气孔用密封材料密封。

36. 发明授权

US08299566B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08299566B2
公开(公告)日：2012-10-30
申请号：US12188236
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L23/48 , H01L21/763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

37. 发明申请

US20120175612A1 TEST STRUCTURE FOR DETERMINATION OF TSV DEPTH 有权
标题翻译：测定TSV深度的测试结构
公开(公告)号：US20120175612A1
公开(公告)日：2012-07-12
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/48
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

38. 发明申请

US20120132992A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20120132992A1
公开(公告)日：2012-05-31
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

39. 发明申请

US20120032737A1 ON-CHIP MILLIMETER WAVE LANGE COUPLER 有权
标题翻译：片上微米波浪耦合器
公开(公告)号：US20120032737A1
公开(公告)日：2012-02-09
申请号：US13277265
申请日：2011-10-20
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H03D3/00 , H03F3/68
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

40. 发明申请

US20100035390A1 METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成高性能FET和高电压FET的方法
公开(公告)号：US20100035390A1
公开(公告)日：2010-02-11
申请号：US12188366
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823462 , H01L21/823481 , H01L27/1203 , H01L27/1207
摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.
摘要翻译：保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

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